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Merge branch 'master' into SDK12

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This commit is contained in:
Gordon Williams 2016-10-04 14:15:58 +01:00
commit a54fdf6bf8
204 changed files with 1480 additions and 25532 deletions
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6
.travis.yml
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@ -17,7 +17,7 @@ before_install:
- sudo apt-get update
- sudo apt-get install libsdl1.2-dev gcc-arm-embedded
- curl -Ls http://s3.voneicken.com/xtensa-lx106-elf-20160330.tgx | tar Jxf -
- curl -Ls http://s3.voneicken.com/esp_iot_sdk_v1.5.0.tgx | tar Jxf -
- curl -Ls http://s3.voneicken.com/esp_iot_sdk_v2.0.0.p1.tgx | tar Jxf -
before_script:
- arm-none-eabi-gcc --version
@ -39,10 +39,10 @@ compiler:
env:
global:
- RELEASE=1
#- RELEASE=1
- TRAVIS=1
- V=0
- ESP8266_SDK_ROOT=$TRAVIS_BUILD_DIR/esp_iot_sdk_v1.5.0
- ESP8266_SDK_ROOT=$TRAVIS_BUILD_DIR/esp_iot_sdk_v2.0.0.p1
- PATH=$PATH:$TRAVIS_BUILD_DIR/xtensa-lx106-elf/bin/
matrix:
- ESP8266_BOARD=1

80
CONTRIBUTING.md
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@ -1,35 +1,78 @@
Contributing
===========
=============
Thanks for thinking about contributing to Espruino! Anything you can add is hugely appreciated, but please can you follow a few simple rules:
* Keep the same coding style (See **Coding Style** below)
Support / Bugs
--------------
First, please try and check that your problem hasn't [already been found](https://github.com/espruino/Espruino/issues) or [covered on our forum](http://www.espruino.com/Forum).
[Submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them: a minimal test case, and an actual and expected result. If you can't come up with these, please [post on the forum](http://www.espruino.com/Forum) first as it may just be something in your code that we can help out with.
Work on Espruino is supported by [sales of our boards](http://www.espruino.com/Order).
**If your board isn't made by us but came pre-installed with Espruino then you should contact the manufacturers.**
We try and support users of the boards we sell, but if you bought a non-official board your issue may not get addressed. In this case, please consider [donating](http://www.espruino.com/Download) to help cover the time it takes to fix problems (even so, we can't guarantee to fix every problem).
Documentation
-------------
Improvements to Documentation are amazingly helpful, and are very rare so hugely appreciated.
### Functions/Variables
If you want to change something in a [built-in function's documentation](http://www.espruino.com/Reference), look at the heading for the function on that page and there will be a right-arrow (⇒).
If you click on that it will bring you to the area of Espruino's source code where the function *and the documentation for it* are stored. You can then edit the documentation in that file (above the function) on GitHub and issue a pull request - it's in Markdown format.
### Tutorials
Please [see here](http://www.espruino.com/Writing+Tutorials)
### Other
If there's something specific to an area of the Espruino interpreter *that can't be put in a source file*, please create a Markdown (`.md`) file in the relevant area, and make sure you link to it from other relevant files so it can be found.
Contributing Code
-----------------
### Modules
Please [see here](http://www.espruino.com/Writing+Modules)
### Espruino code
* Please keep the same coding style (See **Coding Style** below)
* Keep the minimum amount of changes in each pull request/commit (this really helps with debugging later on)
* Try not to commit huge whitespace/refactoring changes along with your fix
* Avoid adding newlines, spaces, refactoring everything or renaming things to your own personal style (some things really could do with renaming, but please check first or we may reject your pull request)
* Ensure that you are not contributing someone else's code, and that you are willing to add your code under Espruino's MPL Licence
* Make sure that what you do doesn't break the Espruino board or the other boards we build for. We can't check all the boards for every commit, so if you break something you'll annoy a whole bunch of people.
* Be aware that Espruino is designed for Microcontrollers - with very low amounts of flash and memory. Both are at a premium so don't statically allocate variables or do other stuff that will use up RAM.
* Avoid randomly adding newlines, spaces, refactoring everything or renaming things to your own personal style (some things really could do with renaming, but please check first or we may reject your pull request)
* Don't add a whole bunch of indirection/abstraction for the sake of it - it'll probably just use of more of our precious memory.
* If you add a new API, try and make it familiar to Arduino/JavaScript users.
* Please [RUN THE TESTS](tests/README.md) before and after your changes to check that there are no regressions
* Finally, please issue us a pull request to [www.github.com/espruino](https://www.github.com/espruino/Espruino) via GitHub. It's way easier for us to incorporate, give credit, and track changes that way.
Target Areas
-----------
We'll keep the outstanding issues in [GitHub's issue list](https://github.com/espruino/Espruino/issues), but general stuff that would really help us is:
* Tests. If something doesn't work, please make a test for it. Even if you don't fix it it'll help others greatly. Bonus points if it's in a pull request :)
* Documentation. Improving the documentation (either the EspruinoDocs project, source code, the auto-generated reference, or the Markdown files in this project) would be fantastic.
* Duplication. If the same code is used for multiple platforms, try and make sure it's shared, not duplicated.
* Remove hard-coded stuff. Some things are still hard-coded with ifdefs for each board - we want all that stuff to be generated from `build_platform_info.py` using the board definition file.
* Speed. There are a few areas this could be improved - but please benchmark what you're doing both before and afterwards on the Espruino board to check that what you've done helps.
* Memory Usage. Both RAM and Flash are at a premium. Ways of reducing this (including stack usage) and making usage more efficient are really appreciated.
* JavaScript compliance (without affecting speed or memory usage too much).
* **Tests** If something doesn't work, please make a test for it. Even if you don't fix it it'll help others greatly. Bonus points if it's in a pull request :)
* **Documentation** Improving the documentation (either the [EspruinoDocs](https://github.com/espruino/EspruinoDocs) project, source code, the auto-generated reference, or the Markdown files in this project) would be fantastic.
* **Duplication** If the same code is used for multiple platforms, try and make sure it's shared, not duplicated.
* **Remove hard-coded stuff** Some things are still hard-coded with ifdefs for each board - we want all that stuff to be generated from `build_platform_info.py` using the board definition file.
* **Speed** There are a few areas this could be improved - but please benchmark what you're doing both before and afterwards on the Espruino board to check that what you've done helps.
* **Memory Usage** Both RAM and Flash are at a premium. Ways of reducing this (including stack usage) and making usage more efficient are really appreciated.
* **JavaScript compliance** - without affecting speed or memory usage too much
Contributing
-----------
* Please [RUN THE TESTS](tests/README.md) to check that there are no regressions
* Issue us a pull request to [www.github.com/espruino](https://www.github.com/espruino/Espruino) via GitHub
* Please keep each request small (just include one fix per request)
Coding Style
-----------
@ -42,6 +85,9 @@ The rough coding style is as follows, but you should get a good idea from the co
* No Tabs used, only spaces
* Use `bool` for booleans - not `int`
* ```//``` comments for single lines, ```/* ... */``` for multiple lines
* Half-hearted Doxygen compatibility: use ```///<``` for function declaration documentation (if on same line), and ```/** ... */``` if doing it right before a function
* Half-hearted Doxygen compatibility: use ```///<``` for function/variable declaration documentation (if on same line), and ```/** ... */``` if doing it right before a function
* If you're adding comments to a function, make sure they're in the header file, and if you are going to add comments in the source, make sure the two match.
* Do not add `setFooBar // This sets the Foo to Bar` style comments to functions/variables. Only add comments if they *add something that is not obvious from the declaration itself*
* Use new lines in code sparingly (only where it really makes sense)

16
ChangeLog
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@ -1,3 +1,19 @@
1v88 : jshSetEventCallback callbacks now get an argument with the channel number
Tab complete now offers a much better set of completions (fix #926)
Fix emitting of events with long names (fix #906)
Ensure 'af_opendrain' pin mode gets remembered when saving (fix #890)
Add second Promise.thenm argument (fix #869)
Fix 'chained' promises (fix #894)
Fixed memory leak when automatically converting a simple object to a String
Added ES6 Template Literals
Initial commit of ES6 arrow functions
Add 'opendrain_pullup' pinMode (including emulation on STM32F1)
Make OneWire use opendrain_pullup (no resistor needed for short runs now)
Add Software I2C (with opendrain_pullup) (ref #549, fix #29)
Cope with new escape codes for home and end on Ubuntu 16.04 (27,91,70/72)
Tweak VGA output back porch to 2ms (so leftmost pixels always on screen)
Fix regression with 2 concurrent waveforms on different pins (fix #930)
1v87 : Add support for compiling with float-abi=hard (even if it doesn't give us real-world benefits)
Add shortcut for quick execution of common call types
Fix BBC micro:bit save() regression from 1v86

188
Makefile
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@ -37,7 +37,6 @@
# RASPBERRYPI=1
# BEAGLEBONE=1
# ARIETTA=1
# LPC1768=1 # beta
# LCTECH_STM32F103RBT6=1 # LC Technology STM32F103RBT6 Ebay boards
# ARMINARM=1
# NUCLEOF401RE=1
@ -502,15 +501,6 @@ USE_CRYPTO=1
USE_NFC=1
USE_CUSTOM_BOOTLOADER=1
else ifdef LPC1768
EMBEDDED=1
MBED=1
BOARD=LPC1768
MBED_GCC_CS_DIR=$(ROOT)/targetlibs/libmbed/LPC1768/GCC_CS
PRECOMPILED_OBJS+=$(MBED_GCC_CS_DIR)/sys.o $(MBED_GCC_CS_DIR)/cmsis_nvic.o $(MBED_GCC_CS_DIR)/system_LPC17xx.o $(MBED_GCC_CS_DIR)/core_cm3.o $(MBED_GCC_CS_DIR)/startup_LPC17xx.o
LIBS+=-L$(MBED_GCC_CS_DIR) -lmbed
OPTIMIZEFLAGS+=-O3
else ifdef ECU
# Gordon's car ECU (extremely beta!)
USE_TRIGGER=1
@ -568,19 +558,19 @@ else ifdef ESP8266_BOARD
EMBEDDED=1
USE_NET=1
USE_TELNET=1
USE_GRAPHICS=1
#USE_GRAPHICS=1
USE_CRYPTO=1
BOARD=ESP8266_BOARD
# Enable link-time optimisations (inlining across files), use -Os 'cause else we end up with
# too large a firmware (-Os is -O2 without optimizations that increase code size)
ifndef DISABLE_LTO
OPTIMIZEFLAGS+=-Os -std=gnu11 -fgnu89-inline -fno-fat-lto-objects -Wl,--allow-multiple-definition
OPTIMIZEFLAGS+=-Os -g -std=gnu11 -fgnu89-inline -fno-fat-lto-objects -Wl,--allow-multiple-definition
#OPTIMIZEFLAGS+=-DLINK_TIME_OPTIMISATION # this actually slows things down!
else
# DISABLE_LTO is necessary in order to analyze static string sizes (see: topstring makefile target)
OPTIMIZEFLAGS+=-Os -std=gnu11 -fgnu89-inline -Wl,--allow-multiple-definition
endif
ESP_FLASH_MAX ?= 491520 # max bin file: 480KB
ESP_FLASH_MAX ?= 479232 # max bin file: 468KB
ifdef FLASH_4MB
ESP_FLASH_SIZE ?= 4 # 4->4MB (512KB+512KB)
@ -809,6 +799,7 @@ src/jspin.c \
src/jsinteractive.c \
src/jsdevices.c \
src/jstimer.c \
src/jsi2c.c \
src/jsspi.c \
src/jshardware_common.c \
$(WRAPPERFILE)
@ -1387,82 +1378,6 @@ ifdef USE_NFC
PRECOMPILED_OBJS += $(NRF5X_SDK_PATH)/components/nfc/t2t_lib/nfc_t2t_lib_gcc.a
endif
ifeq ($(FAMILY), EFM32GG)
EFM32=1
ARCHFLAGS += -mcpu=cortex-m3 -mthumb
GECKO_SDK_PATH=$(ROOT)/targetlibs/Gecko_SDK
ARM = 1
ARM_HAS_OWN_CMSIS = 1
INCLUDE += -I$(GECKO_SDK_PATH)/cmsis/Include
LINKER_FILE = $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/efm32gg.ld
INCLUDE += -I$(ROOT)/targets/efm32
SOURCES += \
targets/efm32/main.c \
targets/efm32/jshardware.c
INCLUDE += -I$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Include
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/inc
# INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/ustimer/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/rtcdrv/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/nvm/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/common/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emlib/inc
TARGETSOURCES += \
$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/startup_efm32gg.c \
$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c \
$(GECKO_SDK_PATH)/emlib/src/em_gpio.c \
$(GECKO_SDK_PATH)/emlib/src/em_cmu.c \
$(GECKO_SDK_PATH)/emlib/src/em_assert.c \
$(GECKO_SDK_PATH)/emlib/src/em_emu.c \
$(GECKO_SDK_PATH)/emlib/src/em_msc.c \
$(GECKO_SDK_PATH)/emlib/src/em_rtc.c \
$(GECKO_SDK_PATH)/emlib/src/em_int.c \
$(GECKO_SDK_PATH)/emlib/src/em_system.c \
$(GECKO_SDK_PATH)/emlib/src/em_timer.c \
$(GECKO_SDK_PATH)/emlib/src/em_usart.c \
$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/src/gpiointerrupt.c \
$(GECKO_SDK_PATH)/emdrv/rtcdrv/src/rtcdriver.c \
$(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c
# $(GECKO_SDK_PATH)/emdrv/ustimer/src/ustimer.c
# $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm.c \
# $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c \
# $(GECKO_SDK_PATH)/emlib/src/em_acmp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_adc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_aes.c \
# $(GECKO_SDK_PATH)/emlib/src/em_burtc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_crc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_cryotimer.c \
# $(GECKO_SDK_PATH)/emlib/src/em_crypto.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dac.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dbg.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dma.c \
# $(GECKO_SDK_PATH)/emlib/src/em_ebi.c \
# $(GECKO_SDK_PATH)/emlib/src/em_i2c.c \
# $(GECKO_SDK_PATH)/emlib/src/em_idac.c \
# $(GECKO_SDK_PATH)/emlib/src/em_lcd.c \
# $(GECKO_SDK_PATH)/emlib/src/em_ldma.c \
# $(GECKO_SDK_PATH)/emlib/src/em_lesense.c \
# $(GECKO_SDK_PATH)/emlib/src/em_letimer.c \
# $(GECKO_SDK_PATH)/emlib/src/em_leuart.c \
# $(GECKO_SDK_PATH)/emlib/src/em_mpu.c \
# $(GECKO_SDK_PATH)/emlib/src/em_opamp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_pcnt.c \
# $(GECKO_SDK_PATH)/emlib/src/em_prs.c \
# $(GECKO_SDK_PATH)/emlib/src/em_rmu.c \
# $(GECKO_SDK_PATH)/emlib/src/em_rtcc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_vcmp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_wdog.c
endif #FAMILY == EFM32
ifdef NRF5X
# Just try and get rid of the compile warnings.
CFLAGS += -Wno-sign-conversion -Wno-conversion -Wno-unused-parameter -fomit-frame-pointer #this is for device manager in nordic sdk
@ -1606,6 +1521,84 @@ ifdef NRF5X
endif #NRF5X
ifeq ($(FAMILY), EFM32GG)
EFM32=1
ARCHFLAGS += -mcpu=cortex-m3 -mthumb
GECKO_SDK_PATH=$(ROOT)/targetlibs/Gecko_SDK
ARM = 1
ARM_HAS_OWN_CMSIS = 1
INCLUDE += -I$(GECKO_SDK_PATH)/cmsis/Include
LINKER_FILE = $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/efm32gg.ld
INCLUDE += -I$(ROOT)/targets/efm32
SOURCES += \
targets/efm32/main.c \
targets/efm32/jshardware.c
INCLUDE += -I$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Include
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/inc
# INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/ustimer/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/rtcdrv/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/nvm/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/common/inc
INCLUDE += -I$(GECKO_SDK_PATH)/emlib/inc
TARGETSOURCES += \
$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/startup_efm32gg.c \
$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c \
$(GECKO_SDK_PATH)/emlib/src/em_gpio.c \
$(GECKO_SDK_PATH)/emlib/src/em_cmu.c \
$(GECKO_SDK_PATH)/emlib/src/em_assert.c \
$(GECKO_SDK_PATH)/emlib/src/em_emu.c \
$(GECKO_SDK_PATH)/emlib/src/em_msc.c \
$(GECKO_SDK_PATH)/emlib/src/em_rtc.c \
$(GECKO_SDK_PATH)/emlib/src/em_int.c \
$(GECKO_SDK_PATH)/emlib/src/em_system.c \
$(GECKO_SDK_PATH)/emlib/src/em_timer.c \
$(GECKO_SDK_PATH)/emlib/src/em_usart.c \
$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/src/gpiointerrupt.c \
$(GECKO_SDK_PATH)/emdrv/rtcdrv/src/rtcdriver.c \
$(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c
# $(GECKO_SDK_PATH)/emdrv/ustimer/src/ustimer.c
# $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm.c \
# $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c \
# $(GECKO_SDK_PATH)/emlib/src/em_acmp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_adc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_aes.c \
# $(GECKO_SDK_PATH)/emlib/src/em_burtc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_crc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_cryotimer.c \
# $(GECKO_SDK_PATH)/emlib/src/em_crypto.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dac.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dbg.c \
# $(GECKO_SDK_PATH)/emlib/src/em_dma.c \
# $(GECKO_SDK_PATH)/emlib/src/em_ebi.c \
# $(GECKO_SDK_PATH)/emlib/src/em_i2c.c \
# $(GECKO_SDK_PATH)/emlib/src/em_idac.c \
# $(GECKO_SDK_PATH)/emlib/src/em_lcd.c \
# $(GECKO_SDK_PATH)/emlib/src/em_ldma.c \
# $(GECKO_SDK_PATH)/emlib/src/em_lesense.c \
# $(GECKO_SDK_PATH)/emlib/src/em_letimer.c \
# $(GECKO_SDK_PATH)/emlib/src/em_leuart.c \
# $(GECKO_SDK_PATH)/emlib/src/em_mpu.c \
# $(GECKO_SDK_PATH)/emlib/src/em_opamp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_pcnt.c \
# $(GECKO_SDK_PATH)/emlib/src/em_prs.c \
# $(GECKO_SDK_PATH)/emlib/src/em_rmu.c \
# $(GECKO_SDK_PATH)/emlib/src/em_rtcc.c \
# $(GECKO_SDK_PATH)/emlib/src/em_vcmp.c \
# $(GECKO_SDK_PATH)/emlib/src/em_wdog.c
endif #FAMILY == EFM32
ifeq ($(FAMILY),ESP8266)
# move os_printf strings into flash to save RAM space
DEFINES += -DUSE_OPTIMIZE_PRINTF
@ -1619,17 +1612,6 @@ CFLAGS+= -fno-builtin \
-Wl,EL -Wl,--gc-sections -nostdlib -mlongcalls -mtext-section-literals
endif
ifdef MBED
ARCHFLAGS += -mcpu=cortex-m3 -mthumb
ARM=1
INCLUDE+=-I$(ROOT)/targetlibs/libmbed -I$(ROOT)/targetlibs/libmbed/$(CHIP) -I$(ROOT)/targetlibs/libmbed/$(CHIP)/GCC_CS
DEFINES += -DMBED
INCLUDE += -I$(ROOT)/targetlibs/mbed
SOURCES += targets/mbed/main.c
CPPSOURCES += targets/mbed/jshardware.cpp
endif
ifdef ARM
ifndef LINKER_FILE # nRF5x targets define their own linker file.
@ -1936,7 +1918,7 @@ PARTIAL = espruino_esp8266_partial.o
LD_SCRIPT1 = ./targets/esp8266/eagle.app.v6.new.1024.app1.ld
LD_SCRIPT2 = ./targets/esp8266/eagle.app.v6.new.1024.app2.ld
APPGEN_TOOL = $(ESP8266_SDK_ROOT)/tools/gen_appbin.py
BOOTLOADER = "$(ESP8266_SDK_ROOT)/bin/boot_v1.4(b1).bin"
BOOTLOADER = $(ESP8266_SDK_ROOT)/bin/boot_v1.6.bin
BLANK = $(ESP8266_SDK_ROOT)/bin/blank.bin
INIT_DATA = $(ESP8266_SDK_ROOT)/bin/esp_init_data_default.bin
@ -1989,7 +1971,7 @@ $(USER2_BIN): $(USER2_ELF) $(USER1_BIN)
$(Q)$(OBJCOPY) --only-section .data -O binary $(USER2_ELF) eagle.app.v6.data.bin
$(Q)$(OBJCOPY) --only-section .rodata -O binary $(USER2_ELF) eagle.app.v6.rodata.bin
$(Q)$(OBJCOPY) --only-section .irom0.text -O binary $(USER2_ELF) eagle.app.v6.irom0text.bin
$(Q)COMPILE=gcc python $(APPGEN_TOOL) $(USER2_ELF) 2 $(ESP_FLASH_MODE) $(ESP_FLASH_FREQ_DIV) $(ESP_FLASH_SIZE) 0 >/dev/null
$(Q)COMPILE=gcc python $(APPGEN_TOOL) $(USER2_ELF) 2 $(ESP_FLASH_MODE) $(ESP_FLASH_FREQ_DIV) $(ESP_FLASH_SIZE) 1 >/dev/null
$(Q) rm -f eagle.app.v6.*.bin
$(Q) mv eagle.app.flash.bin $@
@ -2167,7 +2149,7 @@ endif
clean:
@echo Cleaning targets
$(Q)find . -name \*.o | grep -v libmbed | grep -v arm-bcm2708 | xargs rm -f
$(Q)find . -name \*.o | grep -v arm-bcm2708 | xargs rm -f
$(Q)rm -f $(ROOT)/gen/*.c $(ROOT)/gen/*.h $(ROOT)/gen/*.ld
$(Q)rm -f $(PROJ_NAME).elf
$(Q)rm -f $(PROJ_NAME).hex

34
README.md
View File

@ -13,9 +13,9 @@ http://www.espruino.com &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [
About
-----
Espruino is a JavaScript interpreter for microcontrollers. It is designed to fit into devices with as little as 128kB Flash and 8kB RAM.
Espruino is a JavaScript interpreter for microcontrollers. It is designed for devices with as little as 128kB Flash and 8kB RAM.
Please support Espruino by [ordering one of our official boards](http://www.espruino.com/Order).
Please support Espruino by [ordering one of our official boards](http://www.espruino.com/Order) or [donating](http://www.espruino.com/Download)
Documentation
@ -32,7 +32,7 @@ Builds for the [Espruino Board](http://www.espruino.com/EspruinoBoard) and [Pico
Other documentation of use is:
* [The Forum](http://forum.espruino.com/)
* [FAQ](http://www.espruino.com//FAQ)
* [FAQ](http://www.espruino.com/FAQ)
* [Troubleshooting](http://www.espruino.com/Troubleshooting)
* [Performance Notes](http://www.espruino.com/Performance)
* [Implementation Notes](http://www.espruino.com/Internals)
@ -42,21 +42,27 @@ Other documentation of use is:
* [Hardware Debugging Notes](http://www.espruino.com/AdvancedDebug)
Support / Bugs
--------------
First, please try and check that your problem hasn't [already been found](https://github.com/espruino/Espruino/issues) or [covered on our forum](http://www.espruino.com/Forum).
[Submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them: a **small** test case (not your whole program), and an actual and expected result. If you can't come up with these, please [post on the forum](http://www.espruino.com/Forum) first as it may just be something in your code that we can help out with.
Work on Espruino is supported by [sales of our boards](http://www.espruino.com/Order).
**If your board isn't made by us but came pre-installed with Espruino then you should contact the manufacturers.**
We try and support users of the boards we sell, but if you bought a non-official board your issue may not get addressed. In this case, please consider [donating](http://www.espruino.com/Download) to help cover the time it takes to fix problems (even so, we can't guarantee to fix every problem).
License
-------
Please see the [LICENSE](LICENSE) file
Found a Bug?
------------
Please check that it hasn't [already been found](https://github.com/espruino/Espruino/issues) or [been covered on our forum](http://www.espruino.com/Forum)
Please [submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them (ideally with a test case for the ```tests``` directory). Please be aware that we're very busy, so if you report something (especially if it doesn't contain a test or a pull request) it may not be fixed for quite some time.
Building
Building
--------
Check out [the page on building Espruino](README_Building.md)
@ -95,7 +101,6 @@ If you are a board manufacturer interested in getting your board officially supp
* Carambola - WORKING - GPIO via filesystem (no I2C)
* Raspberry Pi - WORKING - GPIO via filesystem or wiringPi (no I2C)
* Sony SmartWatch - NOT WORKING - USB VCP support for F2 still needed
* MBed platforms - have not worked for a while - full hardware wrapper still required
* LC-TECH STM32F103RBT6 - WORKING, but with some issues (LED inverted logic, BTN needs pullup to work)
* [ST NUCLEO-F401RE](http://www.espruino.com/ReferenceNUCLEOF401RE) - WORKING
* ST NUCLEO-F411RE - WORKING
@ -108,7 +113,7 @@ If you are a board manufacturer interested in getting your board officially supp
Modification
------------
**Check out [the documentation on the build process](README_BuildProcess.md) first** - this should
**Check out [the documentation on the build process](README_BuildProcess.md) first** - this should
clear up a lot of potential questions about the Espruino architecture.
Please see [CONTRIBUTING.md](CONTRIBUTING.md) for some hints about code style/etc.
@ -157,4 +162,3 @@ so because we make money from the sales of Espruino boards. If your users reques
support from us then we have absolutely no obligation to help them. However, we'll
be a lot more motivated if you're actively helping to improve Espruino for all its
users (not just your own).

4
boards/ESP8266_BOARD.py
View File

@ -36,7 +36,7 @@ chip = {
'package' : "",
'ram' : 80,
'flash' : 0,
'speed' : 80,
'speed' : 160,
'usart' : 2,
'spi' : 1,
'i2c' : 1,
@ -46,7 +46,7 @@ chip = {
'address' : 0x78000,
'page_size' : 4096,
'pages' : 3,
'flash_available' : 480, # firmware can be up to this size
'flash_available' : 468, # firmware can be up to this size
},
};
devices = {

2
boards/ESPRUINOWIFI.py
View File

@ -96,6 +96,8 @@ board = {
'left2' : ['A10','A8'],
'_notes' : {
'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole(true)` to avoid",
'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole(true)` to avoid",
'A2' : 'ESP8266 RX',
'A3' : 'ESP8266 TX',
'A15' : 'ESP8266 CTS', # ESP8266 Clear to send (when enabled with AT+UART_DEF)

47
boards/LPC1768.py
View File

@ -1,47 +0,0 @@
#!/bin/false
# This file is part of Espruino, a JavaScript interpreter for Microcontrollers
#
# Copyright (C) 2013 Gordon Williams <gw@pur3.co.uk>
#
# This Source Code Form is subject to the terms of the Mozilla Public
# License, v. 2.0. If a copy of the MPL was not distributed with this
# file, You can obtain one at http://mozilla.org/MPL/2.0/.
#
# ----------------------------------------------------------------------------------------
# This file contains information for a specific board - the available pins, and where LEDs,
# Buttons, and other in-built peripherals are. It is used to build documentation as well
# as various source and header files for Espruino.
# ----------------------------------------------------------------------------------------
import pinutils;
# placeholder
info = {
'name' : "MBed LPC1768",
'link' : [ "http://www.espruino.com/kick" ],
'variables' : 2000, #?
'binary_name' : 'espruino_%v_lpc1768.bin',
'build' : {
'defines' : [
]
}
};
chip = {
'part' : "LPC1768",
'family' : "LPC1768",
# 'package' : "LQFP64",
'ram' : 32,
'flash' : 512,
'speed' : 96,
'usart' : 3,
'spi' : 2,
'i2c' : 2,
'adc' : 6,
'dac' : 0
};
devices = {
};
def get_pins():
return []

4
boards/PICO_R1_3.py
View File

@ -89,8 +89,8 @@ board = {
'top2' : ['VBAT','3.3','GND'],
'right' : ['A4', 'A3', 'A2', 'A1', 'A0', 'A10', 'B9', 'B8'],
'_notes' : {
'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole()` to avoid",
'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole()` to avoid",
'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole(true)` to avoid",
'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole(true)` to avoid",
'A9' : "Connected directly to USB 5V",
'A13' : "Accessible on row of gold SMD pads on underside",
'A14' : "Accessible on row of gold SMD pads on underside",

202
libs/bluetooth/jswrap_bluetooth.c
View File

@ -80,6 +80,7 @@ bool nfcEnabled = false;
#define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */
#define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */
#define MAX_CONN_PARAMS_UPDATE_COUNT 3 /**< Number of attempts before giving up the connection parameter negotiation. */
#define APP_CFG_CHAR_MAX_LEN 20 /**< Size of the characteristic value being notified (in bytes). */
#ifdef USE_BOOTLOADER
#define SEC_PARAM_BOND 1 /**< Perform bonding. */
@ -256,10 +257,8 @@ void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info) {
}
void advertising_start(void) {
uint32_t err_code = 0;
if (bleStatus & BLE_IS_ADVERTISING) return;
// Actually start advertising
ble_gap_adv_params_t adv_params;
memset(&adv_params, 0, sizeof(adv_params));
adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND;
@ -268,8 +267,7 @@ void advertising_start(void) {
adv_params.timeout = APP_ADV_TIMEOUT_IN_SECONDS;
adv_params.interval = advertising_interval;
err_code = sd_ble_gap_adv_start(&adv_params);
// APP_ERROR_CHECK(err_code); // don't bother checking
sd_ble_gap_adv_start(&adv_params);
bleStatus |= BLE_IS_ADVERTISING;
}
@ -693,6 +691,7 @@ static void on_ble_evt(ble_evt_t * p_ble_evt)
switch (p_ble_evt->header.evt_id) {
case BLE_GAP_EVT_TIMEOUT:
// the timeout for sd_ble_gap_adv_start expired - kick it off again
bleStatus &= ~BLE_IS_ADVERTISING; // we still think we're advertising, but we stopped
advertising_start();
break;
@ -1126,7 +1125,6 @@ void jswrap_nrf_bluetooth_sleep(void) {
// Stop advertising
if (bleStatus & BLE_IS_ADVERTISING)
advertising_stop();
NRF_RADIO->TASKS_DISABLE = (1UL);
}
/*JSON{
@ -1138,7 +1136,6 @@ void jswrap_nrf_bluetooth_sleep(void) {
Enable Bluetooth communications (they are enabled by default)
*/
void jswrap_nrf_bluetooth_wake(void) {
// NRF_RADIO->TASKS_DISABLE = (0UL); // BUG: This was causing a hardfault.
advertising_start();
}
@ -1365,6 +1362,7 @@ NRF.setServices({
readable : true, // optional, default is false
writable : true, // optional, default is false
notify : true, // optional, default is false
indicate : true, // optional, default is false
onWrite : function(evt) { // optional
console.log("Got ", evt.data);
}
@ -1429,6 +1427,8 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) {
char_md.char_props.broadcast = 1;
if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "notify", 0)))
char_md.char_props.notify = 1;
if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "indicate", 0)))
char_md.char_props.indicate = 1;
if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "readable", 0)))
char_md.char_props.read = 1;
if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "writable", 0))) {
@ -1490,19 +1490,6 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) {
}
jsvUnLock(charVar);
/* We'd update the characteristic with:
memset(&hvx_params, 0, sizeof(hvx_params));
hvx_params.handle = characteristic_handle.value_handle;
hvx_params.p_data = p_string;
hvx_params.p_len = &length;
hvx_params.type = BLE_GATT_HVX_NOTIFICATION;
return sd_ble_gatts_hvx(p_nus->conn_handle, &hvx_params);
Maybe we could find the handle out based on characteristic UUID, rather than having
to store it?
*/
jsvObjectIteratorNext(&serviceit);
}
@ -1520,6 +1507,181 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) {
}
}
/*JSON{
"type" : "staticmethod",
"class" : "NRF",
"name" : "updateServices",
"generate" : "jswrap_nrf_bluetooth_updateServices",
"params" : [
["data","JsVar","The service (and characteristics) to update"]
]
}
Update values for the services and characteristics Espruino advertises.
Only services and characteristics previously declared using `setServices` are affected.
To update the '0xABCD' characteristic in the '0xBCDE' service:
```
NRF.updateServices({
0xBCDE : {
0xABCD : {
value : "World"
}
}
});
```
To notify connected clients of a change to the '0xABCD' characteristic in the '0xBCDE' service:
```
NRF.updateServices({
0xBCDE : {
0xABCD : {
value : "World",
notify: true
}
}
});
```
This only works if the characteristic was created with `notify: true` using `setServices`,
otherwise the characteristic will be updated but no notification will be sent.
To indicate (i.e. notify with ACK) connected clients of a change to the '0xABCD' characteristic in the '0xBCDE' service:
```
NRF.updateServices({
0xBCDE : {
0xABCD : {
value : "World",
indicate: true
}
}
});
```
This only works if the characteristic was created with `indicate: true` using `setServices`,
otherwise the characteristic will be updated but no notification will be sent.
**Note:** See `setServices` for more information
*/
void jswrap_nrf_bluetooth_updateServices(JsVar *data) {
uint32_t err_code;
if (jsvIsObject(data)) {
JsvObjectIterator it;
jsvObjectIteratorNew(&it, data);
while (jsvObjectIteratorHasValue(&it)) {
ble_uuid_t ble_uuid;
memset(&ble_uuid, 0, sizeof(ble_uuid));
const char *errorStr;
if ((errorStr = bleVarToUUIDAndUnLock(&ble_uuid,
jsvObjectIteratorGetKey(&it)))) {
jsExceptionHere(JSET_ERROR, "Invalid Service UUID: %s", errorStr);
break;
}
JsVar *serviceVar = jsvObjectIteratorGetValue(&it);
JsvObjectIterator serviceit;
jsvObjectIteratorNew(&serviceit, serviceVar);
while (jsvObjectIteratorHasValue(&serviceit)) {
ble_uuid_t char_uuid;
memset(&char_uuid, 0, sizeof(char_uuid));
if ((errorStr = bleVarToUUIDAndUnLock(&char_uuid,
jsvObjectIteratorGetKey(&serviceit)))) {
jsExceptionHere(JSET_ERROR, "Invalid Characteristic UUID: %s",
errorStr);
break;
}
JsVar *charVar = jsvObjectIteratorGetValue(&serviceit);
JsVar *charValue = jsvObjectGetChild(charVar, "value", 0);
bool notification_requested = jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "notify", 0));
bool indication_requested = jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "indicate", 0));
if (charValue) {
JSV_GET_AS_CHAR_ARRAY(vPtr, vLen, charValue);
if (vPtr && vLen) {
uint8_t* p_value = (uint8_t*) vPtr;
uint16_t len = MIN(vLen, APP_CFG_CHAR_MAX_LEN);
// Update value and notify/indicate if appropriate
uint16_t char_handle;
ble_uuid_t uuid_it;
ble_gatts_hvx_params_t hvx_params;
ble_gatts_value_t gatts_value;
// Find the first user characteristic handle
err_code = sd_ble_gatts_initial_user_handle_get(&char_handle);
if (err_code != NRF_SUCCESS) {
APP_ERROR_CHECK(err_code);
}
// Iterate over all handles until the correct UUID or no match is found
// We assume that handles are sequential
while (true) {
memset(&uuid_it, 0, sizeof(uuid_it));
err_code = sd_ble_gatts_attr_get(char_handle, &uuid_it, NULL);
if (err_code == NRF_ERROR_NOT_FOUND) {
// "Out of bounds" => we went over the last known characteristic
break;
} else if (err_code == NRF_SUCCESS) {
// Valid handle => check if UUID matches
if (uuid_it.uuid == char_uuid.uuid) {
// Update the value for subsequent reads even if no client is currently connected
memset(&gatts_value, 0, sizeof(gatts_value));
gatts_value.len = len;
gatts_value.offset = 0;
gatts_value.p_value = p_value;
err_code = sd_ble_gatts_value_set(m_conn_handle, char_handle, &gatts_value);
if (err_code != NRF_SUCCESS) {
APP_ERROR_CHECK(err_code);
}
// Notify/indicate connected clients if necessary
if ((notification_requested || indication_requested) && (m_conn_handle != BLE_CONN_HANDLE_INVALID)) {
memset(&hvx_params, 0, sizeof(hvx_params));
hvx_params.handle = char_handle;
hvx_params.type = indication_requested ? BLE_GATT_HVX_INDICATION : BLE_GATT_HVX_NOTIFICATION;
hvx_params.offset = 0;
hvx_params.p_len = &len;
hvx_params.p_data = p_value;
err_code = sd_ble_gatts_hvx(m_conn_handle, &hvx_params);
if ((err_code != NRF_SUCCESS)
&& (err_code != NRF_ERROR_INVALID_STATE)
&& (err_code != BLE_ERROR_NO_TX_PACKETS)
&& (err_code != BLE_ERROR_GATTS_SYS_ATTR_MISSING)) {
APP_ERROR_CHECK(err_code);
}
}
break;
}
} else {
APP_ERROR_CHECK(err_code);
}
char_handle++;
}
}
}
jsvUnLock(charValue);
jsvUnLock(charVar);
jsvObjectIteratorNext(&serviceit);
}
jsvObjectIteratorFree(&serviceit);
jsvUnLock(serviceVar);
jsvObjectIteratorNext(&it);
}
jsvObjectIteratorFree(&it);
} else if (!jsvIsUndefined(data)) {
jsExceptionHere(JSET_TYPEERROR, "Expecting object or undefined, got %t",
data);
}
}
/*JSON{
"type" : "staticmethod",

1
libs/bluetooth/jswrap_bluetooth.h
View File

@ -26,6 +26,7 @@ void jswrap_nrf_bluetooth_wake(void);
JsVarFloat jswrap_nrf_bluetooth_getBattery(void);
void jswrap_nrf_bluetooth_setAdvertising(JsVar *data, JsVar *options);
void jswrap_nrf_bluetooth_setServices(JsVar *data);
void jswrap_nrf_bluetooth_updateServices(JsVar *data);
void jswrap_nrf_bluetooth_setScan(JsVar *callback);
void jswrap_nrf_bluetooth_setTxPower(JsVarInt pwr);

6
libs/crypto/jswrap_crypto.c
View File

@ -38,7 +38,7 @@
}
Cryptographic functions
**Note:** This library is currently only included in builds for the Espruino Pico. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room.
**Note:** This library is currently only included in builds for the Espruino Pico and Espruino WiFi. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room.
*/
@ -50,7 +50,7 @@ Cryptographic functions
}
Class containing AES encryption/decryption
**Note:** This library is currently only included in builds for the Espruino Pico. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room.
**Note:** This library is currently only included in builds for the Espruino Pico and Espruino WiFi. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room.
*/
/*JSON{
"type" : "staticproperty",
@ -449,4 +449,4 @@ JsVar *jswrap_crypto_AES_encrypt(JsVar *message, JsVar *key, JsVar *options) {
JsVar *jswrap_crypto_AES_decrypt(JsVar *message, JsVar *key, JsVar *options) {
return jswrap_crypto_AEScrypt(message, key, options, false);
}
#endif
#endif

4
libs/network/esp8266/jswrap_esp8266_network.c
View File

@ -1657,7 +1657,7 @@ Perform a network ping request. The parameter can be either a String or a numeri
void jswrap_ESP8266_ping(
JsVar *ipAddr, //!< A string or integer representation of an IP address.
JsVar *pingCallback //!< Optional callback function.
) {
) {
memset(&pingOpt, 0, sizeof(pingOpt));
// If the parameter is a string, get the IP address from the string
// representation.
@ -2001,7 +2001,7 @@ static void wifiEventHandler(System_Event_t *evt) {
int rssi = evt->event_info.ap_probereqrecved.rssi;
if (rssi > 0) rssi = 0;
jsvObjectSetChildAndUnLock(jsDetails, "rssi", jsvNewFromInteger(rssi));
mac = evt->event_info.sta_connected.mac;
mac = evt->event_info.ap_probereqrecved.mac;
os_sprintf(macAddrString, macFmt, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
jsvObjectSetChildAndUnLock(jsDetails, "mac", jsvNewFromString(macAddrString));
sendWifiEvent(evt->event, jsDetails);

13
libs/network/esp8266/ota.c
View File

@ -87,12 +87,13 @@ static void sendResponse(OtaConn *oc, uint16_t code, char *text) {
*
* It returns an error string if something is amiss
*/
static char* check_header(void *buf) {
static char* check_header(void *buf, int which) {
uint8_t *cd = (uint8_t *)buf;
uint32_t *buf32 = buf;
os_printf("OTA hdr %p: %08lX %08lX %08lX %08lX\n", buf, buf32[0], buf32[1], buf32[2], buf32[3]);
if (cd[0] != 0xEA) return "IROM magic missing";
if (cd[1] != 4 || cd[2] > 3 || (cd[3]>>4) > 6) return "bad flash header";
if (cd[3] < 3 && cd[3] != which) return "Wrong partition binary";
if (((uint16_t *)buf)[3] != 0x4010) return "Invalid entry addr";
if (((uint32_t *)buf)[2] != 0) return "Invalid start offset";
return NULL;
@ -153,8 +154,11 @@ static int16_t otaHandleUpload(OtaConn *oc) {
uint16_t toFlash = OTA_CHUNK_SZ;
if (oc->rxBufFill < toFlash) toFlash = oc->rxBufFill;
// let's see which partition we need to flash
uint8 id = system_upgrade_userbin_check();
// check that data starts with an appropriate header
if (err == NULL && offset == 0) err = check_header(oc->rxBuffer+oc->rxBufOff);
if (err == NULL && offset == 0) err = check_header(oc->rxBuffer+oc->rxBufOff, 1-id);
// return an error if there is one
if (err != NULL) {
@ -163,8 +167,7 @@ static int16_t otaHandleUpload(OtaConn *oc) {
return -1;
}
// let's see which partition we need to flash and what flash address that puts us at
uint8 id = system_upgrade_userbin_check();
// let's see which what flash address we're uploading to
uint32_t address = id ? 0x1000 : flashUser2Addr[flashSizeMap];
address += offset;
@ -200,7 +203,7 @@ static int16_t otaHandleReboot(OtaConn *oc) {
uint32 buf[8];
spi_flash_read(address, buf, sizeof(buf));
char *err = check_header(buf);
char *err = check_header(buf, 1-id);
if (err != NULL) {
os_printf("OTA Error %d: %s\n", 400, err);
sendResponse(oc, 400, err);

2
libs/network/jswrap_net.c
View File

@ -468,6 +468,8 @@ You can also:
For more information about generating and using certificates, see:
https://engineering.circle.com/https-authorized-certs-with-node-js/
(You'll need to use 2048 bit certificates as opposed to 4096 bit shown above)
*/
// ---------------------------------------------------------------------------------

17
libs/network/telnet/jswrap_telnet.c
View File

@ -66,7 +66,7 @@ static uint8_t tnSrvMode; // current mode for the telnet server
/*JSON{
"type" : "library",
"class" : "Telnet"
"class" : "TelnetServer"
}
This library implements a telnet console for the Espruino interpreter. It requires a network
connection, e.g. Wifi, and **currently only functions on the ESP8266 and on Linux **. It uses
@ -77,7 +77,7 @@ port 23 on the ESP8266 and port 2323 on Linux.
/*JSON{
"type" : "staticmethod",
"class" : "Telnet",
"class" : "TelnetServer",
"name" : "setOptions",
"generate" : "jswrap_telnet_setOptions",
"params": [
@ -110,7 +110,7 @@ void jswrap_telnet_setOptions(JsVar *jsOptions) {
/*JSON{
"type" : "init",
"class" : "Telnet",
"class" : "TelnetServer",
"generate" : "jswrap_telnet_init"
}
*/
@ -124,7 +124,7 @@ void jswrap_telnet_init(void) {
/*JSON{
"type" : "kill",
"class" : "Telnet",
"class" : "TelnetServer",
"generate" : "jswrap_telnet_kill"
}
*/
@ -134,7 +134,7 @@ void jswrap_telnet_kill(void) {
/*JSON{
"type" : "idle",
"class" : "Telnet",
"class" : "TelnetServer",
"generate" : "jswrap_telnet_idle"
}
*/
@ -226,7 +226,12 @@ void telnetRelease(JsNetwork *net) {
printf("tnSrv: released console from sock %d\n", tnSrv.cliSock);
netCloseSocket(net, tnSrv.cliSock);
tnSrv.cliSock = 0;
if (!jsiIsConsoleDeviceForced()) jsiSetConsoleDevice(tnSrv.oldConsole, false);
IOEventFlags console = jsiGetConsoleDevice();
// only switch away from telnet if the current console is TELNET, this allows the current
// console to be set to something else while connected via telnet and then not have it
// switched again when disconnecting from telnet
if (console == EV_TELNET && !jsiIsConsoleDeviceForced())
jsiSetConsoleDevice(tnSrv.oldConsole, false);
}
// Attempt to send buffer on an established client connection, returns true if it sent something

59
libs/puckjs/jswrap_puck.c
View File

@ -35,6 +35,10 @@
// Has the magnetometer been turned on?
bool mag_enabled = false;
/* TODO: Use software I2C for this instead. Since we're relying
* on the internal pullup resistors there might be some gotchas
* since we force high here for 0.1uS here before going open circuit. */
void wr(int pin, bool state) {
if (state) {
nrf_gpio_pin_set(pin); nrf_gpio_cfg_output(pin);
@ -138,7 +142,6 @@ uint8_t i2c_rd(bool nack) {
return data;
}
// Turn magnetometer on and configure
bool mag_on(int milliHz) {
int reg1 = 0;
@ -172,14 +175,14 @@ bool mag_on(int milliHz) {
reg1 |= 1; // Active bit
i2c_wr(reg1);
i2c_stop();
return true;
return true;
}
// Wait for magnetometer IRQ line to be set
void mag_wait() {
int timeout = I2C_TIMEOUT*2;
while (!nrf_gpio_pin_read(MAG_INT) && --timeout);
if (!timeout) err("Timeout (wait reading)");
if (!timeout) jsExceptionHere(JSET_INTERNALERROR, "Timeout (Magnetometer)");
}
// Read a value
@ -229,6 +232,22 @@ Class containing [Puck.js's](http://www.puck-js.com) utility functions.
"return" : ["JsVar", "An Object `{x,y,z}` of magnetometer readings as integers" ]
}
Turn on the magnetometer, take a single reading, and then turn it off again.
An object of the form `{x,y,z}' is returned containing magnetometer readings.
Due to residual magnetism in the Puck and magnetometer itself, with
no magnetic field the Puck will not return `{x:0,y:0,z:0}`.
Instead, it's up to you to figure out what the 'zero value' is for your
Puck in your location and to then subtract that from the value returned. If
you're not trying to measure the Earth's magnetic field then it's a good idea
to just take a reading at startup and use that.
With the aerial at the top of the board, the `y` reading is vertical, `x` is
horizontal, and `z` is through the board.
Readings are in increments of 0.1 micro Tesla (uT). The Earth's magnetic field
varies from around 25-60 uT, so the reading will vary by 250 to 600 depending
on location.
*/
JsVar *jswrap_puck_mag() {
if (!mag_enabled) mag_on(80000);
@ -247,12 +266,9 @@ JsVar *jswrap_puck_mag() {
Called after `Puck.magOn()` every time magnetometer data
is discovered. There is one argument which is an object
of the form `{x,y,z}' containing magnetometer readings
as integers.
as integers (for more information see `Puck.mag()`.
*/
void _jswrap_mag_irq() {
}
/*JSON{
"type" : "staticmethod",
"class" : "Puck",
@ -396,6 +412,35 @@ int jswrap_puck_capSense(Pin tx, Pin rx) {
return (int)nrf_utils_cap_sense(CAPSENSE_TX_PIN, CAPSENSE_RX_PIN);
}
/*JSON{
"type" : "staticmethod",
"class" : "Puck",
"name" : "light",
"#ifdef" : "NRF52",
"generate" : "jswrap_puck_light",
"return" : ["float", "A light value from 0 to 1" ]
}
Read a light value based on the light the red LED is seeing
*/
JsVarFloat jswrap_puck_light() {
// If pin state wasn't an analog input before, make it one now,
// read, and delay, just to make sure everything has time to settle
// before the 'real' reading
JshPinState s = jshPinGetState(LED1_PININDEX);
if (s != JSHPINSTATE_GPIO_IN) {
jshPinOutput(LED1_PININDEX,0);// discharge
jshPinAnalog(LED1_PININDEX);// analog
jshDelayMicroseconds(5000);
}
JsVarFloat f = jshPinAnalog(LED1_PININDEX)/0.45;
if (f>1) f=1;
// turn the red LED back on if it was on before
if (s & JSHPINSTATE_PIN_IS_ON)
jshPinOutput(LED1_PININDEX, 1);
return f;
}
/*JSON{
"type" : "kill",
"generate" : "jswrap_puck_kill"

1
libs/puckjs/jswrap_puck.h
View File

@ -18,6 +18,7 @@ void jswrap_puck_magOff();
JsVar *jswrap_puck_mag();
void jswrap_puck_IR(JsVar *data);
int jswrap_puck_capSense(Pin tx, Pin rx);
JsVarFloat jswrap_puck_light();
void jswrap_puck_kill();
bool jswrap_puck_idle();

2
libs/tv/tv.c
View File

@ -271,7 +271,7 @@ void tv_vga_irq() {
jshPinSetValue(tvPinSyncV, tvCurrentLine>=2); // 2 lines of sync
jshDelayMicroseconds(1);
jshPinSetValue(tvPinSync, 1);
jshDelayMicroseconds(1);
jshDelayMicroseconds(2);
uint32_t lineIdx = ((uint32_t)tvCurrentLine - 20) / tvLineRepeat; // 20px = front porch
if (lineIdx < tvHeight) {

10
scripts/common.py
View File

@ -313,14 +313,14 @@ def get_prefix_name(jsondata):
def get_ifdef_description(d):
if d=="SAVE_ON_FLASH": return "devices with low flash memory"
if d=="STM32F1": return "STM32F1 devices (including Espruino Board)"
if d=="STM32F1": return "STM32F1 devices (including Original Espruino Board)"
if d=="USE_LCD_SDL": return "Linux with SDL support compiled in"
if d=="USE_TLS": return "devices with TLS and SSL support (Espruino Pico only)"
if d=="USE_TLS": return "devices with TLS and SSL support (Espruino Pico and Espruino WiFi only)"
if d=="RELEASE": return "release builds"
if d=="LINUX": return "Linux-based builds"
if d=="USE_USB_HID": return "devices that support USB HID (Espruino Pico)"
if d=="USE_AES": return "devices that support AES (Espruino Pico, Espruino Wifi or Linux)"
if d=="USE_CRYPTO": return "devices that support Crypto Functionality (Espruino Pico, Espruino Wifi, Linux or ESP8266)"
if d=="USE_USB_HID": return "devices that support USB HID (Espruino Pico and Espruino WiFi)"
if d=="USE_AES": return "devices that support AES (Espruino Pico, Espruino WiFi or Linux)"
if d=="USE_CRYPTO": return "devices that support Crypto Functionality (Espruino Pico, Espruino WiFi, Linux or ESP8266)"
print("WARNING: Unknown ifdef '"+d+"' in common.get_ifdef_description")
return d

2
src/jsdevices.c
View File

@ -319,7 +319,7 @@ void CALLED_FROM_INTERRUPT jshPushIOWatchEvent(
// If there is a callback associated with this GPIO event then invoke
// it and we are done.
if (jshEventCallbacks[channel-EV_EXTI0]) {
jshEventCallbacks[channel-EV_EXTI0](state);
jshEventCallbacks[channel-EV_EXTI0](state, channel);
return;
}

2
src/jsdevices.h
View File

@ -185,7 +185,7 @@ void jshSetFlowControlXON(IOEventFlags device, bool hostShouldTransmit);
void jshSetFlowControlEnabled(IOEventFlags device, bool xOnXOff);
// Functions that can be called in an IRQ when a pin changes state
typedef void(*JshEventCallbackCallback)(bool state);
typedef void(*JshEventCallbackCallback)(bool state, IOEventFlags flags);
/// Set a callback function to be called when an event occurs
void jshSetEventCallback(IOEventFlags channel, JshEventCallbackCallback callback);

10
src/jshardware.h
View File

@ -101,7 +101,8 @@ bool jshPinGetValue(Pin pin); ///< Get the value of a digital input. DOES NOT ch
typedef enum {
JSHPINSTATE_UNDEFINED, ///< Used when getting the pin state, if we have no idea what it is.
JSHPINSTATE_GPIO_OUT, ///< GPIO pin as totem pole output
JSHPINSTATE_GPIO_OUT_OPENDRAIN, ///< GPIO pin as open-collector/open-drain output WITH PULLUP
JSHPINSTATE_GPIO_OUT_OPENDRAIN, ///< GPIO pin as open-collector/open-drain output WITHOUT PULLUP
JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP, ///< GPIO pin as open-collector/open-drain output WITH PULLUP
JSHPINSTATE_GPIO_IN, ///< GPIO pin as input (also tri-stated output)
JSHPINSTATE_GPIO_IN_PULLUP, ///< GPIO pin input with internal pull-up
JSHPINSTATE_GPIO_IN_PULLDOWN, ///< GPIO pin input with internal pull-down
@ -123,6 +124,7 @@ typedef enum {
#define JSHPINSTATE_IS_OUTPUT(state) ( \
(state)==JSHPINSTATE_GPIO_OUT || \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \
(state)==JSHPINSTATE_AF_OUT || \
(state)==JSHPINSTATE_AF_OUT_OPENDRAIN || \
(state)==JSHPINSTATE_USART_OUT || \
@ -132,6 +134,7 @@ typedef enum {
/// Should a pin of this state be Open Drain?
#define JSHPINSTATE_IS_OPENDRAIN(state) ( \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \
(state)==JSHPINSTATE_AF_OUT_OPENDRAIN || \
(state)==JSHPINSTATE_I2C || \
0)
@ -146,6 +149,7 @@ typedef enum {
/// Should a pin of this state have an internal pullup?
#define JSHPINSTATE_IS_PULLUP(state) ( \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \
(state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \
(state)==JSHPINSTATE_GPIO_IN_PULLUP || \
(state)==JSHPINSTATE_USART_IN || \
0)
@ -303,8 +307,8 @@ void jshSPIWait(IOEventFlags device);
typedef struct {
Pin pinSCL;
Pin pinSDA;
int bitrate;
// timeout?
int bitrate; ///< bits per second
bool started; ///< Has I2C 'start' condition been sent so far?
} PACKED_FLAGS JshI2CInfo;
/// Initialise a JshI2CInfo struct to default settings

1
src/jshardware_common.c
View File

@ -38,4 +38,5 @@ void jshI2CInitInfo(JshI2CInfo *inf) {
inf->pinSCL = PIN_UNDEFINED;
inf->pinSDA = PIN_UNDEFINED;
inf->bitrate = 50000; // Is what we used - shouldn't it be 100k?
inf->started = false;
}

168
src/jsi2c.c Normal file
View File

@ -0,0 +1,168 @@
/*
* This file is part of Espruino, a JavaScript interpreter for Microcontrollers
*
* Copyright (C) 2013 Gordon Williams <gw@pur3.co.uk>
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/.
*
* ----------------------------------------------------------------------------
* I2C Utility functions, and software I2C
* ----------------------------------------------------------------------------
*/
#include "jsi2c.h"
#include "jsinteractive.h"
typedef struct {
Pin pinSCL;
Pin pinSDA;
bool started;
int delay;
} i2cInfo;
bool jsi2cPopulateI2CInfo(
JshI2CInfo *inf,
JsVar *options
) {
jshI2CInitInfo(inf);
jsvConfigObject configs[] = {
{"scl", JSV_PIN, &inf->pinSCL},
{"sda", JSV_PIN, &inf->pinSDA},
{"bitrate", JSV_INTEGER, &inf->bitrate}
};
if (jsvReadConfigObject(options, configs, sizeof(configs) / sizeof(jsvConfigObject))) {
return true;
} else
return false;
}
// -------------------------------------------------------- I2C Implementation
const int I2C_TIMEOUT = 100000;
static void dly(i2cInfo *inf) {
volatile int i;
for (i=inf->delay;i>0;i--);
}
static void err(const char *s) {
jsExceptionHere(JSET_ERROR, "I2C Error: %s", s);
}
static void i2c_start(i2cInfo *inf) {
if (inf->started) {
// reset
jshPinSetValue(inf->pinSDA, 1);
dly(inf);
jshPinSetValue(inf->pinSCL, 1);
int timeout = I2C_TIMEOUT;
while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch
if (!timeout) err("Timeout (start)");
dly(inf);
}
if (!jshPinGetValue(inf->pinSDA)) err("Arbitration (start)");
jshPinSetValue(inf->pinSDA, 0);
dly(inf);
jshPinSetValue(inf->pinSCL, 0);
dly(inf);
inf->started = true;
}
static void i2c_stop(i2cInfo *inf) {
jshPinSetValue(inf->pinSDA, 0);
dly(inf);
jshPinSetValue(inf->pinSCL, 1);
int timeout = I2C_TIMEOUT;
while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch
if (!timeout) err("Timeout (stop)");
dly(inf);
jshPinSetValue(inf->pinSDA, 1);
dly(inf);
if (!jshPinGetValue(inf->pinSDA)) err("Arbitration (stop)");
dly(inf);
inf->started = false;
}
static void i2c_wr_bit(i2cInfo *inf, bool b) {
jshPinSetValue(inf->pinSDA, b);
dly(inf);
jshPinSetValue(inf->pinSCL, 1);
dly(inf);
int timeout = I2C_TIMEOUT;
while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch
if (!timeout) err("Timeout (wr)");
jshPinSetValue(inf->pinSCL, 0);
jshPinSetValue(inf->pinSDA, 1); // stop forcing SDA (needed?)
}
static bool i2c_rd_bit(i2cInfo *inf) {
jshPinSetValue(inf->pinSDA, 1); // stop forcing SDA
dly(inf);
jshPinSetValue(inf->pinSCL, 1); // stop forcing SDA
int timeout = I2C_TIMEOUT;
while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch
if (!timeout) err("Timeout (rd)");
dly(inf);
bool b = jshPinGetValue(inf->pinSDA);
jshPinSetValue(inf->pinSCL, 0);
return b;
}
// true on ack, false on nack
static bool i2c_wr(i2cInfo *inf, uint8_t data) {
int i;
for (i=0;i<8;i++) {
i2c_wr_bit(inf, data&128);
data <<= 1;
}
return !i2c_rd_bit(inf);
}
static uint8_t i2c_rd(i2cInfo *inf, bool nack) {
int i;
int data = 0;
for (i=0;i<8;i++)
data = (data<<1) | (i2c_rd_bit(inf)?1:0);
i2c_wr_bit(inf, nack);
return data;
}
static void i2c_initstruct(i2cInfo *inf, JshI2CInfo *i) {
inf->pinSDA = i->pinSDA;
inf->pinSCL = i->pinSCL;
inf->started = i->started;
inf->delay = 4000000/i->bitrate;
}
// ----------------------------------------------------------------------------
void jsi2cWrite(JshI2CInfo *inf, unsigned char address, int nBytes, const unsigned char *data, bool sendStop) {
if (inf->pinSCL==PIN_UNDEFINED || inf->pinSDA==PIN_UNDEFINED)
return;
i2cInfo d;
i2c_initstruct(&d, inf);
i2c_start(&d);
i2c_wr(&d, address<<1);
int i;
for (i=0;i<nBytes;i++)
i2c_wr(&d, data[i]);
if (sendStop) i2c_stop(&d);
inf->started = d.started;
}
void jsi2cRead(JshI2CInfo *inf, unsigned char address, int nBytes, unsigned char *data, bool sendStop) {
if (inf->pinSCL==PIN_UNDEFINED || inf->pinSDA==PIN_UNDEFINED)
return;
i2cInfo d;
i2c_initstruct(&d, inf);
i2c_start(&d);
i2c_wr(&d, 1|(address<<1));
int i;
for (i=0;i<nBytes;i++)
data[i] = i2c_rd(&d, i==nBytes-1);
if (sendStop) i2c_stop(&d);
inf->started = d.started;
}

23
src/jsi2c.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is part of Espruino, a JavaScript interpreter for Microcontrollers
*
* Copyright (C) 2013 Gordon Williams <gw@pur3.co.uk>
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/.
*
* ----------------------------------------------------------------------------
* I2C Utility functions, and software I2C
* ----------------------------------------------------------------------------
*/
#include "jsvar.h"
#include "jshardware.h"
bool jsi2cPopulateI2CInfo(
JshI2CInfo *inf,
JsVar *options
);
void jsi2cWrite(JshI2CInfo *inf, unsigned char address, int nBytes, const unsigned char *data, bool sendStop);
void jsi2cRead(JshI2CInfo *inf, unsigned char address, int nBytes, unsigned char *data, bool sendStop);

21
src/jsinteractive.c
View File

@ -665,13 +665,12 @@ void jsiDumpHardwareInitialisation(vcbprintf_callback user_callback, void *user_
statem == BTN1_PINSTATE) continue;
#endif
// don't bother with normal inputs, as they come up in this state (ish) anyway
const char *s = 0;
// JSHPINSTATE_GPIO_IN is the default - don't do anything for it
if (statem == JSHPINSTATE_GPIO_IN_PULLUP) s="input_pullup";
else if (statem == JSHPINSTATE_GPIO_IN_PULLDOWN) s="input_pulldown";
else if (statem == JSHPINSTATE_GPIO_OUT) s="output";
else if (statem == JSHPINSTATE_GPIO_OUT_OPENDRAIN) s="opendrain";
if (s) cbprintf(user_callback, user_data, "pinMode(%p, \"%s\");\n",pin,s);
if (statem != JSHPINSTATE_GPIO_IN) {
// use getPinMode to get the correct string (remove some duplication)
JsVar *s = jswrap_io_getPinMode(pin);
if (s) cbprintf(user_callback, user_data, "pinMode(%p, %q);\n",pin,s);
jsvUnLock(s);
}
}
}
@ -1345,7 +1344,7 @@ void jsiHandleNewLine(bool execute) {
void jsiHandleChar(char ch) {
// jsiConsolePrintf("[%d:%d]\n", inputState, ch);
//jsiConsolePrintf("[%d:%d]\n", inputState, ch);
//
// special stuff
// 1 - Ctrl-a - beginning of line
@ -1358,6 +1357,8 @@ void jsiHandleChar(char ch) {
// 27 then 91 then 67 ('C') - right
// 27 then 91 then 65 ('A') - up
// 27 then 91 then 66 ('B') - down
// 27 then 91 then 70 - home
// 27 then 91 then 72 - end
//
// 27 then 91 then 48-57 (numeric digits) then 'd' - set line number, used for that
// inputLine and put into any declared functions
@ -1457,7 +1458,9 @@ void jsiHandleChar(char ch) {
jsiChangeToHistory(false); // if at end of line
else
jsiHandleMoveUpDown(1);
}
} else if (ch == 70) jsiHandleEnd();
else if (ch == 72) jsiHandleHome();
else jsiConsolePrintf("[%d:%d]\n", inputState, ch);
} else if (inputState==IS_HAD_27_91_NUMBER) {
if (ch>='0' && ch<='9') {
inputStateNumber = (uint16_t)(10*inputStateNumber + ch - '0');

12
src/jslex.c
View File

@ -170,7 +170,7 @@ const jslJumpTableEnum jslJumpTable[jslJumpTableEnd+1-jslJumpTableStart] = {
JSLJT_TOPHAT, // ^
JSLJT_ID, // _
// 96
JSLJT_SINGLECHAR, // `
JSLJT_STRING, // `
JSLJT_ID, // A lowercase
JSLJT_ID, // B lowercase
JSLJT_ID, // C lowercase
@ -428,7 +428,10 @@ void jslGetNextToken() {
}
}
jsvStringIteratorFree(&it);
lex->tk = lex->currCh==delim ? LEX_STR : LEX_UNFINISHED_STR;
if (lex->currCh==delim) {
lex->tk = delim=='`' ? LEX_TEMPLATE_LITERAL : LEX_STR;
} else
lex->tk = LEX_UNFINISHED_STR;
jslGetNextCh();
} break;
case JSLJT_EXCLAMATION: jslSingleChar();
@ -500,6 +503,9 @@ void jslGetNextToken() {
lex->tk = LEX_TYPEEQUAL;
jslGetNextCh();
}
} else if (lex->currCh=='>') { // =>
lex->tk = LEX_ARROW_FUNCTION;
jslGetNextCh();
} break;
case JSLJT_LESSTHAN: jslSingleChar();
if (lex->currCh=='=') { // <=
@ -618,6 +624,7 @@ void jslTokenAsString(int token, char *str, size_t len) {
case LEX_INT : strncpy(str, "INT", len); return;
case LEX_FLOAT : strncpy(str, "FLOAT", len); return;
case LEX_STR : strncpy(str, "STRING", len); return;
case LEX_TEMPLATE_LITERAL : strncpy(str, "TEMPLATE LITERAL", len); return;
case LEX_UNFINISHED_STR : strncpy(str, "UNFINISHED STRING", len); return;
}
if (token>=LEX_EQUAL && token<LEX_R_LIST_END) {
@ -646,6 +653,7 @@ void jslTokenAsString(int token, char *str, size_t len) {
/* LEX_OREQUAL : */ "|=\0"
/* LEX_OROR : */ "||\0"
/* LEX_XOREQUAL : */ "^=\0"
/* LEX_ARROW_FUNCTION */ "=>\0"
// reserved words
/*LEX_R_IF : */ "if\0"

2
src/jslex.h
View File

@ -24,6 +24,7 @@ typedef enum LEX_TYPES {
LEX_INT,
LEX_FLOAT,
LEX_STR,
LEX_TEMPLATE_LITERAL,
LEX_UNFINISHED_STR,
LEX_UNFINISHED_COMMENT,
@ -51,6 +52,7 @@ typedef enum LEX_TYPES {
LEX_OREQUAL,
LEX_OROR,
LEX_XOREQUAL,
LEX_ARROW_FUNCTION,
// reserved words
#define LEX_R_LIST_START LEX_R_IF
LEX_R_IF,

302
src/jsparse.c
View File

@ -343,62 +343,53 @@ NO_INLINE bool jspeFunctionArguments(JsVar *funcVar) {
return true;
}
NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) {
// actually parse a function... We assume that the LEX_FUNCTION and name
// have already been parsed
JsVar *funcVar = 0;
bool actuallyCreateFunction = JSP_SHOULD_EXECUTE;
if (actuallyCreateFunction)
funcVar = jsvNewWithFlags(JSV_FUNCTION);
JsVar *functionInternalName = 0;
if (parseNamedFunction && lex->tk==LEX_ID) {
// you can do `var a = function foo() { foo(); };` - so cope with this
if (funcVar) functionInternalName = jslGetTokenValueAsVar(lex);
// note that we don't add it to the beginning, because it would mess up our function call code
JSP_ASSERT_MATCH(LEX_ID);
}
// Get arguments save them to the structure
if (!jspeFunctionArguments(funcVar)) {
jsvUnLock2(functionInternalName, funcVar);
// parse failed
return 0;
}
JSP_MATCH_WITH_CLEANUP_AND_RETURN('{',jsvUnLock(funcVar),0);
#ifndef SAVE_ON_FLASH
if (lex->tk==LEX_STR && !strcmp(jslGetTokenValueAsString(lex), "compiled")) {
jsWarn("Function marked with \"compiled\" uploaded in source form");
}
#endif
/* If the function starts with return, treat it specially -
* we don't want to store the 'return' part of it
*/
if (funcVar && lex->tk==LEX_R_RETURN) {
// Parse function, assuming we're on '{'
NO_INLINE bool jspeFunctionDefinitionInternal(JsVar *funcVar, bool expressionOnly) {
if (expressionOnly) {
funcVar->flags = (funcVar->flags & ~JSV_VARTYPEMASK) | JSV_FUNCTION_RETURN;
JSP_ASSERT_MATCH(LEX_R_RETURN);
} else {
JSP_MATCH('{');
#ifndef SAVE_ON_FLASH
if (lex->tk==LEX_STR && !strcmp(jslGetTokenValueAsString(lex), "compiled")) {
jsWarn("Function marked with \"compiled\" uploaded in source form");
}
#endif
/* If the function starts with return, treat it specially -
* we don't want to store the 'return' part of it
*/
if (funcVar && lex->tk==LEX_R_RETURN) {
funcVar->flags = (funcVar->flags & ~JSV_VARTYPEMASK) | JSV_FUNCTION_RETURN;
JSP_ASSERT_MATCH(LEX_R_RETURN);
}
}
// Get the line number (if needed)
JsVarInt lineNumber = 0;
if (actuallyCreateFunction && lex->lineNumberOffset) {
if (funcVar && lex->lineNumberOffset) {
// jslGetLineNumber is slow, so we only do it if we have debug info
lineNumber = (JsVarInt)jslGetLineNumber(lex) + (JsVarInt)lex->lineNumberOffset - 1;
}
// Get the code - parse it and figure out where it stops
JslCharPos funcBegin = jslCharPosClone(&lex->tokenStart);
int brackets = 0;
int lastTokenEnd = -1;
while (lex->tk && (brackets || lex->tk != '}')) {
if (lex->tk == '{') brackets++;
if (lex->tk == '}') brackets--;
lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->it)-1;
JSP_ASSERT_MATCH(lex->tk);
if (!expressionOnly) {
int brackets = 0;
while (lex->tk && (brackets || lex->tk != '}')) {
if (lex->tk == '{') brackets++;
if (lex->tk == '}') brackets--;
lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->it)-1;
JSP_ASSERT_MATCH(lex->tk);
}
} else {
JsExecFlags oldExec = execInfo.execute;
execInfo.execute = EXEC_NO;
jsvUnLock(jspeAssignmentExpression());
execInfo.execute = oldExec;
lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->tokenStart.it)-1;
}
// Then create var and set (if there was any code!)
if (actuallyCreateFunction && lastTokenEnd>0) {
if (funcVar && lastTokenEnd>0) {
// code var
JsVar *funcCodeVar;
if (jsvIsNativeString(lex->sourceVar)) {
@ -426,13 +417,44 @@ NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) {
jsvUnLock2(jsvAddNamedChild(funcVar, funcLineNumber, JSPARSE_FUNCTION_LINENUMBER_NAME), funcLineNumber);
}
}
// if we had a function name, add it to the end
if (functionInternalName)
jsvObjectSetChildAndUnLock(funcVar, JSPARSE_FUNCTION_NAME_NAME, functionInternalName);
}
jslCharPosFree(&funcBegin);
JSP_MATCH_WITH_CLEANUP_AND_RETURN('}',jsvUnLock(funcVar),0);
if (!expressionOnly) JSP_MATCH('}');
return 0;
}
// Parse function (after 'function' has occurred
NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) {
// actually parse a function... We assume that the LEX_FUNCTION and name
// have already been parsed
JsVar *funcVar = 0;
bool actuallyCreateFunction = JSP_SHOULD_EXECUTE;
if (actuallyCreateFunction)
funcVar = jsvNewWithFlags(JSV_FUNCTION);
JsVar *functionInternalName = 0;
if (parseNamedFunction && lex->tk==LEX_ID) {
// you can do `var a = function foo() { foo(); };` - so cope with this
if (funcVar) functionInternalName = jslGetTokenValueAsVar(lex);
// note that we don't add it to the beginning, because it would mess up our function call code
JSP_ASSERT_MATCH(LEX_ID);
}
// Get arguments save them to the structure
if (!jspeFunctionArguments(funcVar)) {
jsvUnLock2(functionInternalName, funcVar);
// parse failed
return 0;
}
// Parse the actual function block
jspeFunctionDefinitionInternal(funcVar, false);
// if we had a function name, add it to the end
if (funcVar && functionInternalName)
jsvObjectSetChildAndUnLock(funcVar, JSPARSE_FUNCTION_NAME_NAME, functionInternalName);
return funcVar;
}
@ -1189,6 +1211,7 @@ NO_INLINE JsVar *jspeFactorObject() {
jslGetNextToken(lex); // skip over current token
} else if (
lex->tk==LEX_STR ||
lex->tk==LEX_TEMPLATE_LITERAL ||
lex->tk==LEX_FLOAT ||
lex->tk==LEX_INT ||
lex->tk==LEX_R_TRUE ||
@ -1318,10 +1341,127 @@ NO_INLINE JsVar *jspeFactorDelete() {
return result;
}
#ifndef SAVE_ON_FLASH
JsVar *jspeTemplateLiteral() {
JsVar *a = 0;
if (JSP_SHOULD_EXECUTE) {
JsVar *template = jslGetTokenValueAsVar(lex);
a = jsvNewFromEmptyString();
if (a && template) {
JsvStringIterator it, dit;
jsvStringIteratorNew(&it, template, 0);
jsvStringIteratorNew(&dit, a, 0);
while (jsvStringIteratorHasChar(&it)) {
char ch = jsvStringIteratorGetChar(&it);
if (ch=='$') {
jsvStringIteratorNext(&it);
ch = jsvStringIteratorGetChar(&it);
if (ch=='{') {
// Now parse out the expression
jsvStringIteratorNext(&it);
int brackets = 1;
JsVar *expr = jsvNewFromEmptyString();
if (!expr) break;
JsvStringIterator eit;
jsvStringIteratorNew(&eit, expr, 0);
while (jsvStringIteratorHasChar(&it)) {
ch = jsvStringIteratorGetChar(&it);
jsvStringIteratorNext(&it);
if (ch=='{') brackets++;
if (ch=='}') {
brackets--;
if (!brackets) break;
}
jsvStringIteratorAppend(&eit, ch);
}
jsvStringIteratorFree(&eit);
JsVar *result = jspEvaluateExpressionVar(expr);
jsvUnLock(expr);
result = jsvAsString(result, true);
jsvStringIteratorAppendString(&dit, result);
jsvUnLock(result);
} else {
jsvStringIteratorAppend(&dit, '$');
}
} else {
jsvStringIteratorAppend(&dit, ch);
jsvStringIteratorNext(&it);
}
}
jsvStringIteratorFree(&it);
jsvStringIteratorFree(&dit);
}
jsvUnLock(template);
}
JSP_ASSERT_MATCH(LEX_TEMPLATE_LITERAL);
return a;
}
#endif
NO_INLINE JsVar *jspeAddNamedFunctionParameter(JsVar *funcVar, JsVar *name) {
if (!funcVar) funcVar = jsvNewWithFlags(JSV_FUNCTION);
char buf[JSLEX_MAX_TOKEN_LENGTH+1];
buf[0] = '\xFF';
jsvGetString(name, &buf[1], JSLEX_MAX_TOKEN_LENGTH);
JsVar *param = jsvAddNamedChild(funcVar, 0, buf);
jsvMakeFunctionParameter(param);
jsvUnLock(param);
return funcVar;
}
#ifndef SAVE_ON_FLASH
// parse an arrow function
NO_INLINE JsVar *jspeArrowFunction(JsVar *funcVar, JsVar *a) {
assert(!a || jsvIsName(a));
JSP_ASSERT_MATCH(LEX_ARROW_FUNCTION);
if (!funcVar) funcVar = jsvNewWithFlags(JSV_FUNCTION);
funcVar = jspeAddNamedFunctionParameter(funcVar, a);
bool expressionOnly = lex->tk!='{';
jspeFunctionDefinitionInternal(funcVar, expressionOnly);
return funcVar;
}
// parse expressions with commas, maybe followed by an arrow function (bracket already matched)
NO_INLINE JsVar *jspeExpressionOrArrowFunction() {
JsVar *a = 0;
JsVar *funcVar = 0;
bool allNames = true;
while (lex->tk!=')' && !JSP_SHOULDNT_PARSE) {
if (allNames && jsvIsName(a))
funcVar = jspeAddNamedFunctionParameter(funcVar, a);
jsvUnLock(a);
a = jspeAssignmentExpression();
if (!jsvIsName(a)) allNames = false;
if (lex->tk!=')') JSP_MATCH_WITH_CLEANUP_AND_RETURN(',', jsvUnLock2(a,funcVar), 0);
}
JSP_MATCH_WITH_CLEANUP_AND_RETURN(')', jsvUnLock2(a,funcVar), 0);
// if arrow is found, create a function
if (allNames && lex->tk==LEX_ARROW_FUNCTION) {
funcVar = jspeArrowFunction(funcVar, a);
jsvUnLock(a);
return funcVar;
} else {
jsvUnLock(funcVar);
return a;
}
}
#endif
NO_INLINE JsVar *jspeFactor() {
if (lex->tk==LEX_ID) {
JsVar *a = jspGetNamedVariable(jslGetTokenValueAsString(lex));
JSP_ASSERT_MATCH(LEX_ID);
#ifndef SAVE_ON_FLASH
if (lex->tk==LEX_TEMPLATE_LITERAL)
jsExceptionHere(JSET_SYNTAXERROR, "Tagged template literals not supported");
else if (lex->tk==LEX_ARROW_FUNCTION && jsvIsName(a)) {
JsVar *funcVar = jspeArrowFunction(0,a);
jsvUnLock(a);
a=funcVar;
}
#endif
return a;
} else if (lex->tk==LEX_INT) {
JsVar *v = 0;
@ -1338,12 +1478,17 @@ NO_INLINE JsVar *jspeFactor() {
JSP_ASSERT_MATCH(LEX_FLOAT);
return v;
} else if (lex->tk=='(') {
JsVar *a = 0;
JSP_ASSERT_MATCH('(');
if (!jspCheckStackPosition()) return 0;
a = jspeExpression();
#ifdef SAVE_ON_FLASH
// Just parse a normal expression (which can include commas)
JsVar *a = jspeExpression();
if (!JSP_SHOULDNT_PARSE) JSP_MATCH_WITH_RETURN(')',a);
return a;
#else
return jspeExpressionOrArrowFunction();
#endif
} else if (lex->tk==LEX_R_TRUE) {
JSP_ASSERT_MATCH(LEX_R_TRUE);
return JSP_SHOULD_EXECUTE ? jsvNewFromBool(true) : 0;
@ -1357,14 +1502,15 @@ NO_INLINE JsVar *jspeFactor() {
JSP_ASSERT_MATCH(LEX_R_UNDEFINED);
return 0;
} else if (lex->tk==LEX_STR) {
if (JSP_SHOULD_EXECUTE) {
JsVar *a = jslGetTokenValueAsVar(lex);
JSP_ASSERT_MATCH(LEX_STR);
return a;
} else {
JSP_ASSERT_MATCH(LEX_STR);
return 0;
}
JsVar *a = 0;
if (JSP_SHOULD_EXECUTE)
a = jslGetTokenValueAsVar(lex);
JSP_ASSERT_MATCH(LEX_STR);
return a;
#ifndef SAVE_ON_FLASH
} else if (lex->tk==LEX_TEMPLATE_LITERAL) {
return jspeTemplateLiteral();
#endif
} else if (lex->tk=='{') {
return jspeFactorObject();
} else if (lex->tk=='[') {
@ -2311,6 +2457,7 @@ NO_INLINE JsVar *jspeStatement() {
lex->tk==LEX_INT ||
lex->tk==LEX_FLOAT ||
lex->tk==LEX_STR ||
lex->tk==LEX_TEMPLATE_LITERAL ||
lex->tk==LEX_R_NEW ||
lex->tk==LEX_R_NULL ||
lex->tk==LEX_R_UNDEFINED ||
@ -2466,6 +2613,22 @@ bool jspIsConstructor(JsVar *constructor, const char *constructorName) {
return isConstructor;
}
/** Get the constructor of the given object, or return 0 if ot found, or not a function */
JsVar *jspGetConstructor(JsVar *object) {
if (!jsvIsObject(object)) return 0;
JsVar *proto = jsvObjectGetChild(object, JSPARSE_INHERITS_VAR, 0);
if (jsvIsObject(proto)) {
JsVar *constr = jsvObjectGetChild(proto, JSPARSE_CONSTRUCTOR_VAR, 0);
if (jsvIsFunction(constr)) {
jsvUnLock(proto);
return constr;
}
jsvUnLock(constr);
}
jsvUnLock(proto);
return 0;
}
// -----------------------------------------------------------------------------
void jspSoftInit() {
@ -2495,6 +2658,22 @@ void jspKill() {
jsvUnLock(r);
}
/** Evaluate the given variable as an expression (in current scope) */
JsVar *jspEvaluateExpressionVar(JsVar *str) {
JsLex lex;
assert(jsvIsString(str));
JsLex *oldLex = jslSetLex(&lex);
jslInit(str);
lex.lineNumberOffset = oldLex->lineNumberOffset;
// actually do the parsing
JsVar *v = jspeExpression();
jslKill();
jslSetLex(oldLex);
return jsvSkipNameAndUnLock(v);
}
/** Execute code form a variable and return the result. If lineNumberOffset
* is nonzero it's added to the line numbers that get reported for errors/debug */
@ -2506,6 +2685,7 @@ JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset) {
jslInit(str);
lex.lineNumberOffset = lineNumberOffset;
JsExecInfo oldExecInfo = execInfo;
execInfo.execute = EXEC_YES;
bool scopeAdded = false;
@ -2529,11 +2709,7 @@ JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset) {
execInfo = oldExecInfo;
// It may have returned a reference, but we just want the value...
if (v) {
return jsvSkipNameAndUnLock(v);
}
// nothing returned
return 0;
return jsvSkipNameAndUnLock(v);
}
JsVar *jspEvaluate(const char *str, bool stringIsStatic) {

4
src/jsparse.h
View File

@ -26,6 +26,8 @@ void jspSoftKill(); ///< used when recovering from or saving to flash
/** Returns true if the constructor function given is the same as that
* of the object with the given name. */
bool jspIsConstructor(JsVar *constructor, const char *constructorName);
/** Get the constructor of the given object, or return 0 if ot found, or not a function */
JsVar *jspGetConstructor(JsVar *object);
/// Create a new built-in object that jswrapper can use to check for built-in functions
JsVar *jspNewBuiltin(const char *name);
@ -53,6 +55,8 @@ JsVar *jspGetException();
/** Return a stack trace string if there was one (and clear it) */
JsVar *jspGetStackTrace();
/** Evaluate the given variable as an expression (in current scope) */
JsVar *jspEvaluateExpressionVar(JsVar *str);
/** Execute code form a variable and return the result. If lineNumberOffset
* is nonzero it's added to the line numbers that get reported for errors/debug */
JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset);

3
src/jstimer.c
View File

@ -129,7 +129,8 @@ void jstUtilTimerInterruptHandler() {
// now search for other tasks writing to this pin... (polyphony)
int t = (utilTimerTasksTail+1) & (UTILTIMERTASK_TASKS-1);
while (t!=utilTimerTasksHead) {
if (UET_IS_BUFFER_WRITE_EVENT(utilTimerTasks[t].type))
if (UET_IS_BUFFER_WRITE_EVENT(utilTimerTasks[t].type) &&
utilTimerTasks[t].data.buffer.pinFunction == task->data.buffer.pinFunction)
sum += ((int)(unsigned int)utilTimerTasks[t].data.buffer.currentValue) - 32768;
t = (t+1) & (UTILTIMERTASK_TASKS-1);
}

11
src/jsutils.c
View File

@ -361,7 +361,16 @@ NO_INLINE void jsAssertFail(const char *file, int line, const char *expr) {
jshTransmitFlush();
NVIC_SystemReset();
#elif defined(ESP8266)
jsiConsolePrint("REBOOTING!\n");
// typically the Espruino console is over telnet, in which case nothing we do here will ever
// show up, so we instead jump through some hoops to print to UART
int os_printf_plus(const char *format, ...) __attribute__((format(printf, 1, 2)));
os_printf_plus("ASSERT FAILED AT %s:%d\n", file,line);
jsiConsolePrint("---console end---\n");
int c, console = jsiGetConsoleDevice();
while ((c=jshGetCharToTransmit(console)) >= 0)
os_printf_plus("%c", c);
os_printf_plus("CRASHING.\n");
*(int*)0xdead = 0xbeef;
extern void jswrap_ESP8266_reboot(void);
jswrap_ESP8266_reboot();
while(1) ;

4
src/jsvar.c
View File

@ -1154,10 +1154,10 @@ JsVar *jsvAsString(JsVar *v, bool unlockVar) {
// Function found and it's not the default one - execute it
JsVar *result = jspExecuteFunction(toStringFn,v,0,0);
jsvUnLock(toStringFn);
return jsvAsString(result, true);
str = jsvAsString(result, true);
} else {
jsvUnLock(toStringFn);
return jsvNewFromString("[object Object]");
str = jsvNewFromString("[object Object]");
}
} else {
const char *constChar = jsvGetConstString(v);

10
src/jsvariterator.c
View File

@ -238,6 +238,16 @@ void jsvStringIteratorAppend(JsvStringIterator *it, char ch) {
jsvSetCharactersInVar(it->var, it->charsInVar);
}
void jsvStringIteratorAppendString(JsvStringIterator *it, JsVar *str) {
JsvStringIterator sit;
jsvStringIteratorNew(&sit, str, 0);
while (jsvStringIteratorHasChar(&sit)) {
jsvStringIteratorAppend(it, jsvStringIteratorGetChar(&sit));
jsvStringIteratorNext(&sit);
}
jsvStringIteratorFree(&sit);
}
// --------------------------------------------------------------------------------------------
void jsvObjectIteratorNew(JsvObjectIterator *it, JsVar *obj) {

3
src/jsvariterator.h
View File

@ -105,6 +105,9 @@ void jsvStringIteratorGotoEnd(JsvStringIterator *it);
/// Append a character TO THE END of a string iterator
void jsvStringIteratorAppend(JsvStringIterator *it, char ch);
/// Append an entire JsVar string TO THE END of a string iterator
void jsvStringIteratorAppendString(JsvStringIterator *it, JsVar *str);
static ALWAYS_INLINE void jsvStringIteratorFree(JsvStringIterator *it) {
jsvUnLock(it->var);
}

2
src/jswrap_espruino.c
View File

@ -61,7 +61,7 @@ Use the STM32's internal thermistor to work out the temperature.
While this is implemented on Espruino boards, it may not be implemented on other devices. If so it'll return NaN.
**Note:** This is not entirely accurate and varies by a few degrees from chip to chip. It measures the **die temperature**, so when connected to USB it could be reading 10 over degrees C above ambient temperature. When running from battery with `setDeepSleep(true)` it is much more accurate though.
*/
*/
/*JSON{
"type" : "staticmethod",

5
src/jswrap_flash.c
View File

@ -523,6 +523,11 @@ bool jsfLoadBootCodeFromFlash(bool isReset) {
if (isReset && !(bootCodeInfo & BOOT_CODE_RUN_ALWAYS)) return false;
code = (char *)(FLASH_DATA_LOCATION);
#ifdef ESP8266
// the flash address is just the offset into the flash chip, but to evaluate the code
// below we need to jump to the memory-mapped window onto flash, so adjust here
code += 0x40200000;
#endif
#endif
jsvUnLock(jspEvaluate(code, true /* We are expecting this ptr to hang around */));
return true;

5
src/jswrap_io.c
View File

@ -345,6 +345,7 @@ Set the mode of the given pin.
* `input_pulldown` - Digital input with internal ~40k pull-down resistor
* `output` - Digital output
* `opendrain` - Digital output that only ever pulls down to 0v. Sending a logical `1` leaves the pin open circuit
* `opendrain_pullup` - Digital output that pulls down to 0v. Sending a logical `1` enables internal ~40k pull-up resistor
* `af_output` - Digital output from built-in peripheral
* `af_opendrain` - Digital output from built-in peripheral that only ever pulls down to 0v.
* Sending a logical `1` leaves the pin open circuit
@ -367,6 +368,7 @@ void jswrap_io_pinMode(
else if (jsvIsStringEqual(mode, "input_pulldown")) m = JSHPINSTATE_GPIO_IN_PULLDOWN;
else if (jsvIsStringEqual(mode, "output")) m = JSHPINSTATE_GPIO_OUT;
else if (jsvIsStringEqual(mode, "opendrain")) m = JSHPINSTATE_GPIO_OUT_OPENDRAIN;
else if (jsvIsStringEqual(mode, "opendrain_pullup")) m = JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP;
else if (jsvIsStringEqual(mode, "af_output")) m = JSHPINSTATE_AF_OUT;
else if (jsvIsStringEqual(mode, "af_opendrain")) m = JSHPINSTATE_AF_OUT_OPENDRAIN;
}
@ -391,7 +393,7 @@ void jswrap_io_pinMode(
],
"return" : ["JsVar","The pin mode, as a string"]
}
Return the current mode of the given pin. See `pinMode` for more information.
Return the current mode of the given pin. See `pinMode` for more information on returned values.
*/
JsVar *jswrap_io_getPinMode(Pin pin) {
if (!jshIsPinValid(pin)) {
@ -407,6 +409,7 @@ JsVar *jswrap_io_getPinMode(Pin pin) {
case JSHPINSTATE_GPIO_IN_PULLDOWN : text = "input_pulldown"; break;
case JSHPINSTATE_GPIO_OUT : text = "output"; break;
case JSHPINSTATE_GPIO_OUT_OPENDRAIN : text = "opendrain"; break;
case JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP : text = "opendrain_pullup"; break;
case JSHPINSTATE_AF_OUT : text = "af_output"; break;
case JSHPINSTATE_AF_OUT_OPENDRAIN : text = "af_opendrain"; break;
default: break;

77
src/jswrap_object.c
View File

@ -172,6 +172,32 @@ Returns an array of all properties (enumerable or not) found directly on a given
**Note:** This doesn't currently work as it should for built-in objects and their prototypes. See bug #380
*/
void _jswrap_object_keys_or_property_names_iterator(
const JswSymList *symbols,
void (*callback)(void *data, JsVar *name),
void *data) {
if (!symbols) return;
unsigned int i;
unsigned char symbolCount = READ_FLASH_UINT8(&symbols->symbolCount);
for (i=0;i<symbolCount;i++) {
unsigned short strOffset = READ_FLASH_UINT16(&symbols->symbols[i].strOffset);
#ifndef USE_FLASH_MEMORY
JsVar *name = jsvNewFromString(&symbols->symbolChars[strOffset]);
#else
// On the esp8266 the string is in flash, so we have to copy it to RAM first
// We can't use flash_strncpy here because it assumes that strings start on a word
// boundary and that's not the case here.
char buf[64], *b = buf, c; const char *s = &symbols->symbolChars[strOffset];
do { c = READ_FLASH_UINT8(s++); *b++ = c; } while (c && b != buf+64);
JsVar *name = jsvNewFromString(buf);
#endif
//os_printf_plus("OBJ cb %s\n", buf);
callback(data, name);
jsvUnLock(name);
}
}
/** This is for Object.keys and Object. However it uses a callback so doesn't allocate anything */
void jswrap_object_keys_or_property_names_cb(
JsVar *obj,
@ -208,43 +234,32 @@ void jswrap_object_keys_or_property_names_cb(
Assume that ALL builtins are non-enumerable. This isn't great but
seems to work quite well right now! */
if (includeNonEnumerable) {
const JswSymList *symbols = 0;
JsVar *protoOwner = jspGetPrototypeOwner(obj);
if (protoOwner) {
// If protoOwner then this is the prototype (protoOwner is the object)
symbols = jswGetSymbolListForObjectProto(protoOwner);
const JswSymList *symbols = jswGetSymbolListForObjectProto(protoOwner);
jsvUnLock(protoOwner);
_jswrap_object_keys_or_property_names_iterator(symbols, callback, data);
} else if (!jsvIsObject(obj) || jsvIsRoot(obj)) {
// get symbols, but only if we're not doing it on a basic object
symbols = jswGetSymbolListForObject(obj);
const JswSymList *symbols = jswGetSymbolListForObject(obj);
_jswrap_object_keys_or_property_names_iterator(symbols, callback, data);
}
while (symbols) {
unsigned int i;
unsigned char symbolCount = READ_FLASH_UINT8(&symbols->symbolCount);
for (i=0;i<symbolCount;i++) {
unsigned short strOffset = READ_FLASH_UINT16(&symbols->symbols[i].strOffset);
#ifndef USE_FLASH_MEMORY
JsVar *name = jsvNewFromString(&symbols->symbolChars[strOffset]);
#else
// On the esp8266 the string is in flash, so we have to copy it to RAM first
// We can't use flash_strncpy here because it assumes that strings start on a word
// boundary and that's not the case here.
char buf[64], *b = buf, c; const char *s = &symbols->symbolChars[strOffset];
do { c = READ_FLASH_UINT8(s++); *b++ = c; } while (c && b != buf+64);
JsVar *name = jsvNewFromString(buf);
#endif
//os_printf_plus("OBJ cb %s\n", buf);
callback(data, name);
jsvUnLock(name);
}
symbols = 0;
if (includePrototype) {
includePrototype = false;
symbols = jswGetSymbolListForObjectProto(obj);
if (includePrototype) {
if (jsvIsObject(obj)) {
JsVar *proto = jsvObjectGetChild(obj, JSPARSE_INHERITS_VAR, 0);
while (jsvIsObject(proto)) {
const JswSymList *symbols = jswGetSymbolListForObjectProto(proto);
_jswrap_object_keys_or_property_names_iterator(symbols, callback, data);
JsVar *p2 = jsvObjectGetChild(proto, JSPARSE_INHERITS_VAR, 0);
jsvUnLock(proto);
proto = p2;
}
}
// finally include Object/String/etc
const JswSymList *symbols = jswGetSymbolListForObjectProto(obj);
_jswrap_object_keys_or_property_names_iterator(symbols, callback, data);
}
if (jsvIsArray(obj) || jsvIsString(obj)) {
@ -622,7 +637,7 @@ void jswrap_object_emit(JsVar *parent, JsVar *event, JsVar *argArray) {
jsWarn("First argument to EventEmitter.emit(..) must be a string");
return;
}
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event);
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event);
if (!eventName) return; // no memory
// extract data
@ -678,7 +693,7 @@ void jswrap_object_removeListener(JsVar *parent, JsVar *event, JsVar *callback)
}
if (jsvIsString(event)) {
// remove the whole child containing listeners
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event);
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event);
if (!eventName) return; // no memory
JsVar *eventListName = jsvFindChildFromVar(parent, eventName, true);
jsvUnLock(eventName);
@ -722,7 +737,7 @@ void jswrap_object_removeAllListeners(JsVar *parent, JsVar *event) {
}
if (jsvIsString(event)) {
// remove the whole child containing listeners
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event);
JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event);
if (!eventName) return; // no memory
JsVar *eventList = jsvFindChildFromVar(parent, eventName, true);

6
src/jswrap_onewire.c
View File

@ -31,7 +31,7 @@ static Pin onewire_getpin(JsVar *parent) {
/** Reset one-wire, return true if a device was present */
static bool NO_INLINE OneWireReset(Pin pin) {
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN);
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP);
//jshInterruptOff();
jshPinSetValue(pin, 0);
jshDelayMicroseconds(500);
@ -45,7 +45,7 @@ static bool NO_INLINE OneWireReset(Pin pin) {
/** Write 'bits' bits, and return what was read (to read, you must send all 1s) */
static JsVarInt NO_INLINE OneWireRead(Pin pin, int bits) {
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN);
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP);
JsVarInt result = 0;
JsVarInt mask = 1;
while (bits-- > 0) {
@ -66,7 +66,7 @@ static JsVarInt NO_INLINE OneWireRead(Pin pin, int bits) {
/** Write 'bits' bits, and return what was read (to read, you must send all 1s) */
static void NO_INLINE OneWireWrite(Pin pin, int bits, unsigned long long data) {
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN);
jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP);
unsigned long long mask = 1;
while (bits-- > 0) {
if (data & mask) { // short pulse

138
src/jswrap_promise.c
View File

@ -24,6 +24,41 @@
#define JS_PROMISE_RESULT_NAME JS_HIDDEN_CHAR_STR"res"
/*
var p = new Promise( function(resolve) { resolve(1); });
p.then( function(value) {
console.log("A"+value); // 1
return value + 1;
}).then( function(value) {
console.log(value); // 2
return new Promise( function( resolve ) { resolve( 4 ); } );
}).then( function( value ) {
console.log( value ); // 4
} );
p.then(function(value) {
console.log("B"+value); // 1
});
produces:
A1
2
4
Should produce
A1
B1
2
4
Basically .then should return a new promise, rather than returning the same one.
_jswrap_promise_resolve should then execute every promise in the list.
*/
/*JSON{
"type" : "class",
"class" : "Promise",
@ -32,11 +67,73 @@
This is the built-in class for ES6 Promises
*/
void _jswrap_promise_resolve(JsVar *promise, JsVar *data) {
JsVar *fn = jsvObjectGetChild(promise, JS_PROMISE_THEN_NAME, 0);
jsiExecuteEventCallback(promise, fn, 1, &data);
void _jswrap_promise_queueresolve(JsVar *promise, JsVar *data);
void _jswrap_promise_add(JsVar *parent, JsVar *callback, const char *name);
void _jswrap_promise_resolve_or_reject(JsVar *promise, JsVar *data, JsVar *fn) {
JsVar *result = 0;
if (jsvIsArray(fn)) {
JsvObjectIterator it;
jsvObjectIteratorNew(&it, fn);
bool first = true;
while (jsvObjectIteratorHasValue(&it)) {
JsVar *f = jsvObjectIteratorGetValue(&it);
JsVar *v = jspExecuteFunction(f, promise, 1, &data);
if (first) {
first = false;
result = v;
} else jsvUnLock(v);
jsvUnLock(f);
jsvObjectIteratorNext(&it);
}
jsvObjectIteratorFree(&it);
} else if (fn) {
result = jspExecuteFunction(fn, promise, 1, &data);
}
jsvObjectSetChild(promise, JS_PROMISE_THEN_NAME, 0); // remove 'resolve' and 'reject' handlers
jsvObjectSetChild(promise, JS_PROMISE_CATCH_NAME, 0); // remove 'resolve' and 'reject' handlers
JsVar *chainedPromise = jsvObjectGetChild(promise, "chain", 0);
jsvObjectSetChild(promise, "chain", 0); // unlink chain
if (chainedPromise) {
JsVar *constr = jspGetConstructor(result);
if (constr && (void*)constr->varData.native.ptr==(void*)jswrap_promise_constructor) {
// if we were given a promise, loop its 'then' in here
JsVar *fn = jsvNewNativeFunction((void (*)(void))_jswrap_promise_queueresolve, JSWAT_VOID|JSWAT_THIS_ARG|(JSWAT_JSVAR<<JSWAT_BITS));
if (fn) {
jsvObjectSetChild(fn, JSPARSE_FUNCTION_THIS_NAME, chainedPromise);
_jswrap_promise_add(result, fn, JS_PROMISE_THEN_NAME);
jsvUnLock(fn);
}
} else {
_jswrap_promise_queueresolve(chainedPromise, result);
}
jsvUnLock(constr);
}
jsvUnLock2(result, chainedPromise);
}
void _jswrap_promise_resolve_or_reject_chain(JsVar *promise, JsVar *data, const char *eventName) {
JsVar *fn = jsvObjectGetChild(promise, eventName, 0);
// if we didn't have a catch, traverse the chain looking for one
if (!fn) {
JsVar *chainedPromise = jsvObjectGetChild(promise, "chain", 0);
while (chainedPromise) {
fn = jsvObjectGetChild(chainedPromise, eventName, 0);
if (fn) {
_jswrap_promise_resolve_or_reject(chainedPromise, data, fn);
jsvUnLock2(fn, chainedPromise);
return;
}
JsVar *n = jsvObjectGetChild(chainedPromise, "chain", 0);
jsvUnLock(chainedPromise);
chainedPromise = n;
}
}
if (fn) _jswrap_promise_resolve_or_reject(promise, data, fn);
jsvUnLock(fn);
}
void _jswrap_promise_resolve(JsVar *promise, JsVar *data) {
_jswrap_promise_resolve_or_reject_chain(promise, data, JS_PROMISE_THEN_NAME);
}
void _jswrap_promise_queueresolve(JsVar *promise, JsVar *data) {
JsVar *fn = jsvNewNativeFunction((void (*)(void))_jswrap_promise_resolve, JSWAT_VOID|JSWAT_THIS_ARG|(JSWAT_JSVAR<<JSWAT_BITS));
if (!fn) return;
@ -46,9 +143,7 @@ void _jswrap_promise_queueresolve(JsVar *promise, JsVar *data) {
}
void _jswrap_promise_reject(JsVar *promise, JsVar *data) {
JsVar *fn = jsvObjectGetChild(promise, JS_PROMISE_CATCH_NAME, 0);
jsiExecuteEventCallback(promise, fn, 1, &data);
jsvUnLock(fn);
_jswrap_promise_resolve_or_reject_chain(promise, data, JS_PROMISE_CATCH_NAME);
}
void _jswrap_promise_queuereject(JsVar *promise, JsVar *data) {
JsVar *fn = jsvNewNativeFunction((void (*)(void))_jswrap_promise_reject, JSWAT_VOID|JSWAT_THIS_ARG|(JSWAT_JSVAR<<JSWAT_BITS));
@ -142,8 +237,7 @@ JsVar *jswrap_promise_all(JsVar *arr) {
jsvObjectIteratorNew(&it, arr);
while (jsvObjectIteratorHasValue(&it)) {
JsVar *p = jsvObjectIteratorGetValue(&it);
jsvUnLock(jswrap_promise_then(p, resolve));
jsvUnLock(jswrap_promise_catch(p, reject));
jsvUnLock(jswrap_promise_then(p, resolve, reject));
jsvUnLock(p);
promises++;
jsvObjectIteratorNext(&it);
@ -221,6 +315,15 @@ void _jswrap_promise_add(JsVar *parent, JsVar *callback, const char *name) {
}
}
static JsVar *jswrap_promise_get_chained_promise(JsVar *parent) {
JsVar *chainedPromise = jsvObjectGetChild(parent, "chain", 0);
if (!chainedPromise) {
chainedPromise = jspNewObject(0, "Promise");
jsvObjectSetChild(parent, "chain", chainedPromise);
}
return chainedPromise;
}
/*JSON{
"type" : "method",
"class" : "Promise",
@ -228,14 +331,17 @@ void _jswrap_promise_add(JsVar *parent, JsVar *callback, const char *name) {
"ifndef" : "SAVE_ON_FLASH",
"generate" : "jswrap_promise_then",
"params" : [
["callback","JsVar","A callback that is called when this promise is resolved"]
["onFulfilled","JsVar","A callback that is called when this promise is resolved"],
["onRejected","JsVar","A callback that is called when this promise is rejected (or nothing)"]
],
"return" : ["JsVar","The original Promise"]
}
*/
JsVar *jswrap_promise_then(JsVar *parent, JsVar *callback) {
_jswrap_promise_add(parent, callback, JS_PROMISE_THEN_NAME);
return jsvLockAgain(parent);
JsVar *jswrap_promise_then(JsVar *parent, JsVar *onFulfilled, JsVar *onRejected) {
_jswrap_promise_add(parent, onFulfilled, JS_PROMISE_THEN_NAME);
if (onRejected)
_jswrap_promise_add(parent, onRejected, JS_PROMISE_CATCH_NAME);
return jswrap_promise_get_chained_promise(parent);
}
/*JSON{
@ -245,12 +351,12 @@ JsVar *jswrap_promise_then(JsVar *parent, JsVar *callback) {
"ifndef" : "SAVE_ON_FLASH",
"generate" : "jswrap_promise_catch",
"params" : [
["callback","JsVar","A callback that is called when this promise is rejected"]
["onRejected","JsVar","A callback that is called when this promise is rejected"]
],
"return" : ["JsVar","The original Promise"]
}
*/
JsVar *jswrap_promise_catch(JsVar *parent, JsVar *callback) {
_jswrap_promise_add(parent, callback, JS_PROMISE_CATCH_NAME);
return jsvLockAgain(parent);
JsVar *jswrap_promise_catch(JsVar *parent, JsVar *onRejected) {
_jswrap_promise_add(parent, onRejected, JS_PROMISE_CATCH_NAME);
return jswrap_promise_get_chained_promise(parent);
}

4
src/jswrap_promise.h
View File

@ -17,5 +17,5 @@ JsVar *jswrap_promise_constructor(JsVar *executor);
JsVar *jswrap_promise_all(JsVar *arr);
JsVar *jswrap_promise_reject(JsVar *data);
JsVar *jswrap_promise_resolve(JsVar *data);
JsVar *jswrap_promise_then(JsVar *parent, JsVar *callback);
JsVar *jswrap_promise_catch(JsVar *parent, JsVar *callback);
JsVar *jswrap_promise_then(JsVar *parent, JsVar *onFulfilled, JsVar *onRejected);
JsVar *jswrap_promise_catch(JsVar *parent, JsVar *onRejected);

69
src/jswrap_spi_i2c.c
View File

@ -14,6 +14,7 @@
* ----------------------------------------------------------------------------
*/
#include "jsspi.h"
#include "jsi2c.h"
#include "jswrap_spi_i2c.h"
#include "jsdevices.h"
#include "jsinteractive.h"
@ -463,6 +464,19 @@ This class allows use of the built-in I2C ports. Currently it allows I2C Master
All addresses are in 7 bit format. If you have an 8 bit address then you need to shift it one bit to the right.
*/
/*JSON{
"type" : "constructor",
"class" : "I2C",
"name" : "I2C",
"generate" : "jswrap_i2c_constructor"
}
Create a software I2C port. This has limited functionality (no baud rate), but it can work on any pins.
Use `SPI.setup` to configure this port.
*/
JsVar *jswrap_i2c_constructor() {
return jsvNewObject();
}
/*JSON{
"type" : "staticmethod",
@ -521,17 +535,21 @@ If not specified in options, the default pins are used (usually the lowest numbe
*/
void jswrap_i2c_setup(JsVar *parent, JsVar *options) {
IOEventFlags device = jsiGetDeviceFromClass(parent);
if (!DEVICE_IS_I2C(device)) return;
JshI2CInfo inf;
jshI2CInitInfo(&inf);
jsvConfigObject configs[] = {
{"scl", JSV_PIN, &inf.pinSCL},
{"sda", JSV_PIN, &inf.pinSDA},
{"bitrate", JSV_INTEGER, &inf.bitrate}
};
if (jsvReadConfigObject(options, configs, sizeof(configs) / sizeof(jsvConfigObject))) {
jshI2CSetup(device, &inf);
if (jsi2cPopulateI2CInfo(&inf, options)) {
if (DEVICE_IS_I2C(device)) {
jshI2CSetup(device, &inf);
} else if (device == EV_NONE) {
// software mode - at least configure pins properly
if (inf.pinSCL != PIN_UNDEFINED) {
jshPinSetValue(inf.pinSCL, 1);
jshPinSetState(inf.pinSCL, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP);
}
if (inf.pinSDA != PIN_UNDEFINED) {
jshPinSetValue(inf.pinSDA, 1);
jshPinSetState(inf.pinSDA, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP);
}
}
// Set up options, so we can initialise it on startup
if (options)
jsvUnLock(jsvSetNamedChild(parent, options, DEVICE_OPTIONS_NAME));
@ -567,15 +585,26 @@ Transmit to the slave device with the given address. This is like Arduino's begi
void jswrap_i2c_writeTo(JsVar *parent, JsVar *addressVar, JsVar *args) {
IOEventFlags device = jsiGetDeviceFromClass(parent);
if (!DEVICE_IS_I2C(device)) return;
bool sendStop = true;
int address = i2c_get_address(addressVar, &sendStop);
JSV_GET_AS_CHAR_ARRAY( dataPtr, dataLen, args);
if (dataPtr && dataLen)
jshI2CWrite(device, (unsigned char)address, (int)dataLen, (unsigned char*)dataPtr, sendStop);
if (dataPtr && dataLen) {
if (DEVICE_IS_I2C(device)) {
jshI2CWrite(device, (unsigned char)address, (int)dataLen, (unsigned char*)dataPtr, sendStop);
} else if (device == EV_NONE) {
// software
JshI2CInfo inf;
JsVar *options = jsvObjectGetChild(parent, DEVICE_OPTIONS_NAME, 0);
if (jsi2cPopulateI2CInfo(&inf, options)) {
inf.started = jsvGetBoolAndUnLock(jsvObjectGetChild(parent, "started", 0));
jsi2cWrite(&inf, (unsigned char)address, (int)dataLen, (unsigned char*)dataPtr, sendStop);
}
jsvUnLock2(jsvObjectSetChild(parent, "started", jsvNewFromBool(inf.started)), options);
}
}
}
/*JSON{
@ -594,7 +623,6 @@ Request bytes from the given slave device, and return them as a Uint8Array (pack
*/
JsVar *jswrap_i2c_readFrom(JsVar *parent, JsVar *addressVar, int nBytes) {
IOEventFlags device = jsiGetDeviceFromClass(parent);
if (!DEVICE_IS_I2C(device)) return 0;
bool sendStop = true;
int address = i2c_get_address(addressVar, &sendStop);
@ -607,7 +635,18 @@ JsVar *jswrap_i2c_readFrom(JsVar *parent, JsVar *addressVar, int nBytes) {
}
unsigned char *buf = (unsigned char *)alloca((size_t)nBytes);
jshI2CRead(device, (unsigned char)address, nBytes, buf, sendStop);
if (DEVICE_IS_I2C(device)) {
jshI2CRead(device, (unsigned char)address, nBytes, buf, sendStop);
} else if (device == EV_NONE) {
// software
JshI2CInfo inf;
JsVar *options = jsvObjectGetChild(parent, DEVICE_OPTIONS_NAME, 0);
if (jsi2cPopulateI2CInfo(&inf, options)) {
inf.started = jsvGetBoolAndUnLock(jsvObjectGetChild(parent, "started", 0));
jsi2cRead(&inf, (unsigned char)address, nBytes, buf, sendStop);
}
jsvUnLock2(jsvObjectSetChild(parent, "started", jsvNewFromBool(inf.started)), options);
} else return 0;
JsVar *array = jsvNewTypedArray(ARRAYBUFFERVIEW_UINT8, nBytes);
if (array) {

1
src/jswrap_spi_i2c.h
View File

@ -21,6 +21,7 @@ void jswrap_spi_send4bit(JsVar *parent, JsVar *srcdata, int bit0, int bit1, Pin
void jswrap_spi_send8bit(JsVar *parent, JsVar *srcdata, int bit0, int bit1, Pin nss_pin);
void jswrap_spi_write(JsVar *parent, JsVar *args);
JsVar *jswrap_i2c_constructor();
void jswrap_i2c_setup(JsVar *parent, JsVar *options);
void jswrap_i2c_writeTo(JsVar *parent, JsVar *addressVar, JsVar *data);
JsVar *jswrap_i2c_readFrom(JsVar *parent, JsVar *addressVar, int nBytes);

5
targetlibs/libmbed/.hg_archival.txt
View File

@ -1,5 +0,0 @@
repo: 82220227f4fa1ef7c958ac22d55b44f198cd91dd
node: b3110cd2dd17dae341d7f8574bd0b6a53060be4d
branch: default
latesttag: null
latesttagdistance: 64

103
targetlibs/libmbed/AnalogIn.h
View File

@ -1,103 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGIN_H
#define MBED_ANALOGIN_H
#include "platform.h"
#if DEVICE_ANALOGIN
#include "analogin_api.h"
namespace mbed {
/** An analog input, used for reading the voltage on a pin
*
* Example:
* @code
* // Print messages when the AnalogIn is greater than 50%
*
* #include "mbed.h"
*
* AnalogIn temperature(p20);
*
* int main() {
* while(1) {
* if(temperature > 0.5) {
* printf("Too hot! (%f)", temperature.read());
* }
* }
* }
* @endcode
*/
class AnalogIn {
public:
/** Create an AnalogIn, connected to the specified pin
*
* @param pin AnalogIn pin to connect to
* @param name (optional) A string to identify the object
*/
AnalogIn(PinName pin) {
analogin_init(&_adc, pin);
}
/** Read the input voltage, represented as a float in the range [0.0, 1.0]
*
* @returns A floating-point value representing the current input voltage, measured as a percentage
*/
float read() {
return analogin_read(&_adc);
}
/** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @returns
* 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
*/
unsigned short read_u16() {
return analogin_read_u16(&_adc);
}
#ifdef MBED_OPERATORS
/** An operator shorthand for read()
*
* The float() operator can be used as a shorthand for read() to simplify common code sequences
*
* Example:
* @code
* float x = volume.read();
* float x = volume;
*
* if(volume.read() > 0.25) { ... }
* if(volume > 0.25) { ... }
* @endcode
*/
operator float() {
return read();
}
#endif
protected:
analogin_t _adc;
};
} // namespace mbed
#endif
#endif

121
targetlibs/libmbed/AnalogOut.h
View File

@ -1,121 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ANALOGOUT_H
#define MBED_ANALOGOUT_H
#include "platform.h"
#if DEVICE_ANALOGOUT
#include "analogout_api.h"
namespace mbed {
/** An analog output, used for setting the voltage on a pin
*
* Example:
* @code
* // Make a sawtooth output
*
* #include "mbed.h"
*
* AnalogOut tri(p18);
* int main() {
* while(1) {
* tri = tri + 0.01;
* wait_us(1);
* if(tri == 1) {
* tri = 0;
* }
* }
* }
* @endcode
*/
class AnalogOut {
public:
/** Create an AnalogOut connected to the specified pin
*
* @param AnalogOut pin to connect to (18)
*/
AnalogOut(PinName pin) {
analogout_init(&_dac, pin);
}
/** Set the output voltage, specified as a percentage (float)
*
* @param value A floating-point value representing the output voltage,
* specified as a percentage. The value should lie between
* 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
* Values outside this range will be saturated to 0.0f or 1.0f.
*/
void write(float value) {
analogout_write(&_dac, value);
}
/** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
*
* @param value 16-bit unsigned short representing the output voltage,
* normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
*/
void write_u16(unsigned short value) {
analogout_write_u16(&_dac, value);
}
/** Return the current output voltage setting, measured as a percentage (float)
*
* @returns
* A floating-point value representing the current voltage being output on the pin,
* measured as a percentage. The returned value will lie between
* 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
*
* @note
* This value may not match exactly the value set by a previous write().
*/
float read() {
return analogout_read(&_dac);
}
#ifdef MBED_OPERATORS
/** An operator shorthand for write()
*/
AnalogOut& operator= (float percent) {
write(percent);
return *this;
}
AnalogOut& operator= (AnalogOut& rhs) {
write(rhs.read());
return *this;
}
/** An operator shorthand for read()
*/
operator float() {
return read();
}
#endif
protected:
dac_t _dac;
};
} // namespace mbed
#endif
#endif

67
targetlibs/libmbed/BusIn.h
View File

@ -1,67 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSIN_H
#define MBED_BUSIN_H
#include "platform.h"
#include "DigitalIn.h"
namespace mbed {
/** A digital input bus, used for reading the state of a collection of pins
*/
class BusIn {
public:
/* Group: Configuration Methods */
/** Create an BusIn, connected to the specified pins
*
* @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusIn(PinName pins[16]);
virtual ~BusIn();
/** Read the value of the input bus
*
* @returns
* An integer with each bit corresponding to the value read from the associated DigitalIn pin
*/
int read();
#ifdef MBED_OPERATORS
/** A shorthand for read()
*/
operator int();
#endif
protected:
DigitalIn* _pin[16];
};
} // namespace mbed
#endif

93
targetlibs/libmbed/BusInOut.h
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@ -1,93 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSINOUT_H
#define MBED_BUSINOUT_H
#include "DigitalInOut.h"
namespace mbed {
/** A digital input output bus, used for setting the state of a collection of pins
*/
class BusInOut {
public:
/** Create an BusInOut, connected to the specified pins
*
* @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusInOut(PinName pins[16]);
virtual ~BusInOut();
/* Group: Access Methods */
/** Write the value to the output bus
*
* @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
*/
void write(int value);
/** Read the value currently output on the bus
*
* @returns
* An integer with each bit corresponding to associated DigitalInOut pin setting
*/
int read();
/** Set as an output
*/
void output();
/** Set as an input
*/
void input();
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone
*/
void mode(PinMode pull);
#ifdef MBED_OPERATORS
/** A shorthand for write()
*/
BusInOut& operator= (int v);
BusInOut& operator= (BusInOut& rhs);
/** A shorthand for read()
*/
operator int();
#endif
protected:
DigitalInOut* _pin[16];
};
} // namespace mbed
#endif

76
targetlibs/libmbed/BusOut.h
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@ -1,76 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUSOUT_H
#define MBED_BUSOUT_H
#include "DigitalOut.h"
namespace mbed {
/** A digital output bus, used for setting the state of a collection of pins
*/
class BusOut {
public:
/** Create an BusOut, connected to the specified pins
*
* @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
*
* @note
* It is only required to specify as many pin variables as is required
* for the bus; the rest will default to NC (not connected)
*/
BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
BusOut(PinName pins[16]);
virtual ~BusOut();
/** Write the value to the output bus
*
* @param value An integer specifying a bit to write for every corresponding DigitalOut pin
*/
void write(int value);
/** Read the value currently output on the bus
*
* @returns
* An integer with each bit corresponding to associated DigitalOut pin setting
*/
int read();
#ifdef MBED_OPERATORS
/** A shorthand for write()
*/
BusOut& operator= (int v);
BusOut& operator= (BusOut& rhs);
/** A shorthand for read()
*/
operator int();
#endif
protected:
DigitalOut* _pin[16];
};
} // namespace mbed
#endif

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targetlibs/libmbed/CAN.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CAN_H
#define MBED_CAN_H
#include "platform.h"
#if DEVICE_CAN
#include "can_api.h"
#include "can_helper.h"
#include "FunctionPointer.h"
namespace mbed {
/** CANMessage class
*/
class CANMessage : public CAN_Message {
public:
/** Creates empty CAN message.
*/
CANMessage() {
len = 8;
type = CANData;
format = CANStandard;
id = 0;
memset(data, 0, 8);
}
/** Creates CAN message with specific content.
*/
CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
len = _len & 0xF;
type = _type;
format = _format;
id = _id;
memcpy(data, _data, _len);
}
/** Creates CAN remote message.
*/
CANMessage(int _id, CANFormat _format = CANStandard) {
len = 0;
type = CANRemote;
format = _format;
id = _id;
memset(data, 0, 8);
}
};
/** A can bus client, used for communicating with can devices
*/
class CAN {
public:
/** Creates an CAN interface connected to specific pins.
*
* @param rd read from transmitter
* @param td transmit to transmitter
*
* Example:
* @code
* #include "mbed.h"
*
* Ticker ticker;
* DigitalOut led1(LED1);
* DigitalOut led2(LED2);
* CAN can1(p9, p10);
* CAN can2(p30, p29);
*
* char counter = 0;
*
* void send() {
* if(can1.write(CANMessage(1337, &counter, 1))) {
* printf("Message sent: %d\n", counter);
* counter++;
* }
* led1 = !led1;
* }
*
* int main() {
* ticker.attach(&send, 1);
* CANMessage msg;
* while(1) {
* if(can2.read(msg)) {
* printf("Message received: %d\n\n", msg.data[0]);
* led2 = !led2;
* }
* wait(0.2);
* }
* }
* @endcode
*/
CAN(PinName rd, PinName td);
virtual ~CAN();
/** Set the frequency of the CAN interface
*
* @param hz The bus frequency in hertz
*
* @returns
* 1 if successful,
* 0 otherwise
*/
int frequency(int hz);
/** Write a CANMessage to the bus.
*
* @param msg The CANMessage to write.
*
* @returns
* 0 if write failed,
* 1 if write was successful
*/
int write(CANMessage msg);
/** Read a CANMessage from the bus.
*
* @param msg A CANMessage to read to.
*
* @returns
* 0 if no message arrived,
* 1 if message arrived
*/
int read(CANMessage &msg);
/** Reset CAN interface.
*
* To use after error overflow.
*/
void reset();
/** Puts or removes the CAN interface into silent monitoring mode
*
* @param silent boolean indicating whether to go into silent mode or not
*/
void monitor(bool silent);
/** Returns number of read errors to detect read overflow errors.
*/
unsigned char rderror();
/** Returns number of write errors to detect write overflow errors.
*/
unsigned char tderror();
/** Attach a function to call whenever a CAN frame received interrupt is
* generated.
*
* @param fptr A pointer to a void function, or 0 to set as none
*/
void attach(void (*fptr)(void));
/** Attach a member function to call whenever a CAN frame received interrupt
* is generated.
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
*/
template<typename T>
void attach(T* tptr, void (T::*mptr)(void)) {
if((mptr != NULL) && (tptr != NULL)) {
_rxirq.attach(tptr, mptr);
setup_interrupt();
} else {
remove_interrupt();
}
}
private:
can_t _can;
FunctionPointer _rxirq;
void setup_interrupt(void);
void remove_interrupt(void);
};
} // namespace mbed
#endif
#endif // MBED_CAN_H

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targetlibs/libmbed/DigitalIn.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIGITALIN_H
#define MBED_DIGITALIN_H
#include "platform.h"
#include "gpio_api.h"
namespace mbed {
/** A digital input, used for reading the state of a pin
*
* Example:
* @code
* // Flash an LED while a DigitalIn is true
*
* #include "mbed.h"
*
* DigitalIn enable(p5);
* DigitalOut led(LED1);
*
* int main() {
* while(1) {
* if(enable) {
* led = !led;
* }
* wait(0.25);
* }
* }
* @endcode
*/
class DigitalIn {
public:
/** Create a DigitalIn connected to the specified pin
*
* @param pin DigitalIn pin to connect to
* @param name (optional) A string to identify the object
*/
DigitalIn(PinName pin) {
gpio_init(&gpio, pin, PIN_INPUT);
}
/** Read the input, represented as 0 or 1 (int)
*
* @returns
* An integer representing the state of the input pin,
* 0 for logical 0, 1 for logical 1
*/
int read() {
return gpio_read(&gpio);
}
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone, OpenDrain
*/
void mode(PinMode pull) {
gpio_mode(&gpio, pull);
}
#ifdef MBED_OPERATORS
/** An operator shorthand for read()
*/
operator int() {
return read();
}
#endif
protected:
gpio_t gpio;
};
} // namespace mbed
#endif

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targetlibs/libmbed/DigitalInOut.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIGITALINOUT_H
#define MBED_DIGITALINOUT_H
#include "platform.h"
#include "gpio_api.h"
namespace mbed {
/** A digital input/output, used for setting or reading a bi-directional pin
*/
class DigitalInOut {
public:
/** Create a DigitalInOut connected to the specified pin
*
* @param pin DigitalInOut pin to connect to
*/
DigitalInOut(PinName pin) {
gpio_init(&gpio, pin, PIN_INPUT);
}
/** Set the output, specified as 0 or 1 (int)
*
* @param value An integer specifying the pin output value,
* 0 for logical 0, 1 (or any other non-zero value) for logical 1
*/
void write(int value) {
gpio_write(&gpio, value);
}
/** Return the output setting, represented as 0 or 1 (int)
*
* @returns
* an integer representing the output setting of the pin if it is an output,
* or read the input if set as an input
*/
int read() {
return gpio_read(&gpio);
}
/** Set as an output
*/
void output() {
gpio_dir(&gpio, PIN_OUTPUT);
}
/** Set as an input
*/
void input() {
gpio_dir(&gpio, PIN_INPUT);
}
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone, OpenDrain
*/
void mode(PinMode pull) {
gpio_mode(&gpio, pull);
}
#ifdef MBED_OPERATORS
/** A shorthand for write()
*/
DigitalInOut& operator= (int value) {
write(value);
return *this;
}
DigitalInOut& operator= (DigitalInOut& rhs) {
write(rhs.read());
return *this;
}
/** A shorthand for read()
*/
operator int() {
return read();
}
#endif
protected:
gpio_t gpio;
};
} // namespace mbed
#endif

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targetlibs/libmbed/DigitalOut.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIGITALOUT_H
#define MBED_DIGITALOUT_H
#include "platform.h"
#include "gpio_api.h"
namespace mbed {
/** A digital output, used for setting the state of a pin
*
* Example:
* @code
* // Toggle a LED
* #include "mbed.h"
*
* DigitalOut led(LED1);
*
* int main() {
* while(1) {
* led = !led;
* wait(0.2);
* }
* }
* @endcode
*/
class DigitalOut {
public:
/** Create a DigitalOut connected to the specified pin
*
* @param pin DigitalOut pin to connect to
*/
DigitalOut(PinName pin) {
gpio_init(&gpio, pin, PIN_OUTPUT);
}
/** Set the output, specified as 0 or 1 (int)
*
* @param value An integer specifying the pin output value,
* 0 for logical 0, 1 (or any other non-zero value) for logical 1
*/
void write(int value) {
gpio_write(&gpio, value);
}
/** Return the output setting, represented as 0 or 1 (int)
*
* @returns
* an integer representing the output setting of the pin,
* 0 for logical 0, 1 for logical 1
*/
int read() {
return gpio_read(&gpio);
}
#ifdef MBED_OPERATORS
/** A shorthand for write()
*/
DigitalOut& operator= (int value) {
write(value);
return *this;
}
DigitalOut& operator= (DigitalOut& rhs) {
write(rhs.read());
return *this;
}
/** A shorthand for read()
*/
operator int() {
return read();
}
#endif
protected:
gpio_t gpio;
};
} // namespace mbed
#endif

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targetlibs/libmbed/DirHandle.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DIRHANDLE_H
#define MBED_DIRHANDLE_H
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
# define NAME_MAX 255
typedef int mode_t;
#else
# include <sys/syslimits.h>
#endif
#include "FileHandle.h"
struct dirent {
char d_name[NAME_MAX+1];
};
namespace mbed {
/** Represents a directory stream. Objects of this type are returned
* by a FileSystemLike's opendir method. Implementations must define
* at least closedir, readdir and rewinddir.
*
* If a FileSystemLike class defines the opendir method, then the
* directories of an object of that type can be accessed by
* DIR *d = opendir("/example/directory") (or opendir("/example")
* to open the root of the filesystem), and then using readdir(d) etc.
*
* The root directory is considered to contain all FileLike and
* FileSystemLike objects, so the DIR* returned by opendir("/") will
* reflect this.
*/
class DirHandle {
public:
/** Closes the directory.
*
* @returns
* 0 on success,
* -1 on error.
*/
virtual int closedir()=0;
/** Return the directory entry at the current position, and
* advances the position to the next entry.
*
* @returns
* A pointer to a dirent structure representing the
* directory entry at the current position, or NULL on reaching
* end of directory or error.
*/
virtual struct dirent *readdir()=0;
/** Resets the position to the beginning of the directory.
*/
virtual void rewinddir()=0;
/** Returns the current position of the DirHandle.
*
* @returns
* the current position,
* -1 on error.
*/
virtual off_t telldir() { return -1; }
/** Sets the position of the DirHandle.
*
* @param location The location to seek to. Must be a value returned by telldir.
*/
virtual void seekdir(off_t location) { }
virtual ~DirHandle() {}
};
} // namespace mbed
typedef mbed::DirHandle DIR;
extern "C" {
DIR *opendir(const char*);
struct dirent *readdir(DIR *);
int closedir(DIR*);
void rewinddir(DIR*);
long telldir(DIR*);
void seekdir(DIR*, long);
int mkdir(const char *name, mode_t n);
};
#endif /* MBED_DIRHANDLE_H */

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targetlibs/libmbed/Ethernet.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ETHERNET_H
#define MBED_ETHERNET_H
#include "platform.h"
#if DEVICE_ETHERNET
namespace mbed {
/** An ethernet interface, to use with the ethernet pins.
*
* Example:
* @code
* // Read destination and source from every ethernet packet
*
* #include "mbed.h"
*
* Ethernet eth;
*
* int main() {
* char buf[0x600];
*
* while(1) {
* int size = eth.receive();
* if(size > 0) {
* eth.read(buf, size);
* printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
* buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
* printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
* buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
* }
*
* wait(1);
* }
* }
* @endcode
*/
class Ethernet {
public:
/** Initialise the ethernet interface.
*/
Ethernet();
/** Powers the hardware down.
*/
virtual ~Ethernet();
enum Mode {
AutoNegotiate,
HalfDuplex10,
FullDuplex10,
HalfDuplex100,
FullDuplex100
};
/** Writes into an outgoing ethernet packet.
*
* It will append size bytes of data to the previously written bytes.
*
* @param data An array to write.
* @param size The size of data.
*
* @returns
* The number of written bytes.
*/
int write(const char *data, int size);
/** Send an outgoing ethernet packet.
*
* After filling in the data in an ethernet packet it must be send.
* Send will provide a new packet to write to.
*
* @returns
* 0 if the sending was failed,
* 1 if the package is successfully sent.
*/
int send();
/** Recevies an arrived ethernet packet.
*
* Receiving an ethernet packet will drop the last received ethernet packet
* and make a new ethernet packet ready to read.
* If no ethernet packet is arrived it will return 0.
*
* @returns
* 0 if no ethernet packet is arrived,
* or the size of the arrived packet.
*/
int receive();
/** Read from an recevied ethernet packet.
*
* After receive returnd a number bigger than 0it is
* possible to read bytes from this packet.
* Read will write up to size bytes into data.
*
* It is possible to use read multible times.
* Each time read will start reading after the last read byte before.
*
* @returns
* The number of byte read.
*/
int read(char *data, int size);
/** Gives the ethernet address of the mbed.
*
* @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
*/
void address(char *mac);
/** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
*
* @returns
* 0 if no ethernet link is pressent,
* 1 if an ethernet link is pressent.
*
* Example:
* @code
* // Using the Ethernet link function
* #include "mbed.h"
*
* Ethernet eth;
*
* int main() {
* wait(1); // Needed after startup.
* if (eth.link()) {
* printf("online\n");
* } else {
* printf("offline\n");
* }
* }
* @endcode
*/
int link();
/** Sets the speed and duplex parameters of an ethernet link
*
* - AutoNegotiate Auto negotiate speed and duplex
* - HalfDuplex10 10 Mbit, half duplex
* - FullDuplex10 10 Mbit, full duplex
* - HalfDuplex100 100 Mbit, half duplex
* - FullDuplex100 100 Mbit, full duplex
*
* @param mode the speed and duplex mode to set the link to:
*/
void set_link(Mode mode);
};
} // namespace mbed
#endif
#endif

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targetlibs/libmbed/FileBase.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FILEBASE_H
#define MBED_FILEBASE_H
typedef int FILEHANDLE;
#include <stdio.h>
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
# define O_RDONLY 0
# define O_WRONLY 1
# define O_RDWR 2
# define O_CREAT 0x0200
# define O_TRUNC 0x0400
# define O_APPEND 0x0008
# define NAME_MAX 255
typedef int mode_t;
typedef int ssize_t;
typedef long off_t;
#else
# include <sys/fcntl.h>
# include <sys/types.h>
# include <sys/syslimits.h>
#endif
#include "platform.h"
namespace mbed {
typedef enum {
FilePathType,
FileSystemPathType
} PathType;
class FileBase {
public:
FileBase(const char *name, PathType t);
virtual ~FileBase();
const char* getName(void);
PathType getPathType(void);
static FileBase *lookup(const char *name, unsigned int len);
static FileBase *get(int n);
protected:
static FileBase *_head;
FileBase *_next;
const char *_name;
PathType _path_type;
};
} // namespace mbed
#endif

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targetlibs/libmbed/FileHandle.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FILEHANDLE_H
#define MBED_FILEHANDLE_H
typedef int FILEHANDLE;
#include <stdio.h>
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
typedef int ssize_t;
typedef long off_t;
#else
# include <sys/types.h>
#endif
namespace mbed {
/** An OO equivalent of the internal FILEHANDLE variable
* and associated _sys_* functions.
*
* FileHandle is an abstract class, needing at least sys_write and
* sys_read to be implmented for a simple interactive device.
*
* No one ever directly tals to/instanciates a FileHandle - it gets
* created by FileSystem, and wrapped up by stdio.
*/
class FileHandle {
public:
/** Write the contents of a buffer to the file
*
* @param buffer the buffer to write from
* @param length the number of characters to write
*
* @returns
* The number of characters written (possibly 0) on success, -1 on error.
*/
virtual ssize_t write(const void* buffer, size_t length) = 0;
/** Close the file
*
* @returns
* Zero on success, -1 on error.
*/
virtual int close() = 0;
/** Function read
* Reads the contents of the file into a buffer
*
* @param buffer the buffer to read in to
* @param length the number of characters to read
*
* @returns
* The number of characters read (zero at end of file) on success, -1 on error.
*/
virtual ssize_t read(void* buffer, size_t length) = 0;
/** Check if the handle is for a interactive terminal device.
* If so, line buffered behaviour is used by default
*
* @returns
* 1 if it is a terminal,
* 0 otherwise
*/
virtual int isatty() = 0;
/** Move the file position to a given offset from a given location.
*
* @param offset The offset from whence to move to
* @param whence SEEK_SET for the start of the file, SEEK_CUR for the
* current file position, or SEEK_END for the end of the file.
*
* @returns
* new file position on success,
* -1 on failure or unsupported
*/
virtual off_t lseek(off_t offset, int whence) = 0;
/** Flush any buffers associated with the FileHandle, ensuring it
* is up to date on disk
*
* @returns
* 0 on success or un-needed,
* -1 on error
*/
virtual int fsync() = 0;
virtual off_t flen() {
/* remember our current position */
off_t pos = lseek(0, SEEK_CUR);
if(pos == -1) return -1;
/* seek to the end to get the file length */
off_t res = lseek(0, SEEK_END);
/* return to our old position */
lseek(pos, SEEK_SET);
return res;
}
virtual ~FileHandle();
};
} // namespace mbed
#endif

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targetlibs/libmbed/FileLike.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FILELIKE_H
#define MBED_FILELIKE_H
#include "FileBase.h"
#include "FileHandle.h"
namespace mbed {
/* Class FileLike
* A file-like object is one that can be opened with fopen by
* fopen("/name", mode). It is intersection of the classes Base and
* FileHandle.
*/
class FileLike : public FileHandle, public FileBase {
public:
/* Constructor FileLike
*
* Variables
* name - The name to use to open the file.
*/
FileLike(const char *name);
virtual ~FileLike();
};
} // namespace mbed
#endif

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targetlibs/libmbed/FilePath.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FILEPATH_H
#define MBED_FILEPATH_H
#include "platform.h"
#include "FileSystemLike.h"
#include "FileLike.h"
namespace mbed {
class FilePath {
public:
FilePath(const char* file_path);
const char* fileName(void);
bool isFileSystem(void);
FileSystemLike* fileSystem(void);
bool isFile(void);
FileLike* file(void);
private:
const char* file_name;
FileBase* fb;
};
} // namespace mbed
#endif

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targetlibs/libmbed/FileSystemLike.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FILESYSTEMLIKE_H
#define MBED_FILESYSTEMLIKE_H
#include "platform.h"
#include "FileBase.h"
#include "FileHandle.h"
#include "DirHandle.h"
namespace mbed {
/** A filesystem-like object is one that can be used to open files
* though it by fopen("/name/filename", mode)
*
* Implementations must define at least open (the default definitions
* of the rest of the functions just return error values).
*/
class FileSystemLike : public FileBase {
public:
/** FileSystemLike constructor
*
* @param name The name to use for the filesystem.
*/
FileSystemLike(const char *name);
virtual ~FileSystemLike();
static DirHandle *opendir();
friend class BaseDirHandle;
/** Opens a file from the filesystem
*
* @param filename The name of the file to open.
* @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
* zero or more of O_CREAT, O_TRUNC, or O_APPEND.
*
* @returns
* A pointer to a FileHandle object representing the
* file on success, or NULL on failure.
*/
virtual FileHandle *open(const char *filename, int flags) = 0;
/** Remove a file from the filesystem.
*
* @param filename the name of the file to remove.
* @param returns 0 on success, -1 on failure.
*/
virtual int remove(const char *filename) { return -1; };
/** Rename a file in the filesystem.
*
* @param oldname the name of the file to rename.
* @param newname the name to rename it to.
*
* @returns
* 0 on success,
* -1 on failure.
*/
virtual int rename(const char *oldname, const char *newname) { return -1; };
/** Opens a directory in the filesystem and returns a DirHandle
* representing the directory stream.
*
* @param name The name of the directory to open.
*
* @returns
* A DirHandle representing the directory stream, or
* NULL on failure.
*/
virtual DirHandle *opendir(const char *name) { return NULL; };
/** Creates a directory in the filesystem.
*
* @param name The name of the directory to create.
* @param mode The permissions to create the directory with.
*
* @returns
* 0 on success,
* -1 on failure.
*/
virtual int mkdir(const char *name, mode_t mode) { return -1; }
// TODO other filesystem functions (mkdir, rm, rn, ls etc)
};
} // namespace mbed
#endif

84
targetlibs/libmbed/FunctionPointer.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FUNCTIONPOINTER_H
#define MBED_FUNCTIONPOINTER_H
#include <string.h>
namespace mbed {
/** A class for storing and calling a pointer to a static or member void function
*/
class FunctionPointer {
public:
/** Create a FunctionPointer, attaching a static function
*
* @param function The void static function to attach (default is none)
*/
FunctionPointer(void (*function)(void) = 0);
/** Create a FunctionPointer, attaching a member function
*
* @param object The object pointer to invoke the member function on (i.e. the this pointer)
* @param function The address of the void member function to attach
*/
template<typename T>
FunctionPointer(T *object, void (T::*member)(void)) {
attach(object, member);
}
/** Attach a static function
*
* @param function The void static function to attach (default is none)
*/
void attach(void (*function)(void) = 0);
/** Attach a member function
*
* @param object The object pointer to invoke the member function on (i.e. the this pointer)
* @param function The address of the void member function to attach
*/
template<typename T>
void attach(T *object, void (T::*member)(void)) {
_object = static_cast<void*>(object);
memcpy(_member, (char*)&member, sizeof(member));
_membercaller = &FunctionPointer::membercaller<T>;
_function = 0;
}
/** Call the attached static or member function
*/
void call();
private:
template<typename T>
static void membercaller(void *object, char *member) {
T* o = static_cast<T*>(object);
void (T::*m)(void);
memcpy((char*)&m, member, sizeof(m));
(o->*m)();
}
void (*_function)(void); // static function pointer - 0 if none attached
void *_object; // object this pointer - 0 if none attached
char _member[16]; // raw member function pointer storage - converted back by registered _membercaller
void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object
};
} // namespace mbed
#endif

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targetlibs/libmbed/I2C.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_I2C_H
#define MBED_I2C_H
#include "platform.h"
#if DEVICE_I2C
#include "i2c_api.h"
namespace mbed {
/** An I2C Master, used for communicating with I2C slave devices
*
* Example:
* @code
* // Read from I2C slave at address 0x62
*
* #include "mbed.h"
*
* I2C i2c(p28, p27);
*
* int main() {
* int address = 0x62;
* char data[2];
* i2c.read(address, data, 2);
* }
* @endcode
*/
class I2C {
public:
enum RxStatus {
NoData,
MasterGeneralCall,
MasterWrite,
MasterRead
};
enum Acknowledge {
NoACK = 0,
ACK = 1
};
/** Create an I2C Master interface, connected to the specified pins
*
* @param sda I2C data line pin
* @param scl I2C clock line pin
*/
I2C(PinName sda, PinName scl);
/** Set the frequency of the I2C interface
*
* @param hz The bus frequency in hertz
*/
void frequency(int hz);
/** Read from an I2C slave
*
* Performs a complete read transaction. The bottom bit of
* the address is forced to 1 to indicate a read.
*
* @param address 8-bit I2C slave address [ addr | 1 ]
* @param data Pointer to the byte-array to read data in to
* @param length Number of bytes to read
* @param repeated Repeated start, true - don't send stop at end
*
* @returns
* 0 on success (ack),
* non-0 on failure (nack)
*/
int read(int address, char *data, int length, bool repeated = false);
/** Read a single byte from the I2C bus
*
* @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
*
* @returns
* the byte read
*/
int read(int ack);
/** Write to an I2C slave
*
* Performs a complete write transaction. The bottom bit of
* the address is forced to 0 to indicate a write.
*
* @param address 8-bit I2C slave address [ addr | 0 ]
* @param data Pointer to the byte-array data to send
* @param length Number of bytes to send
* @param repeated Repeated start, true - do not send stop at end
*
* @returns
* 0 on success (ack),
* non-0 on failure (nack)
*/
int write(int address, const char *data, int length, bool repeated = false);
/** Write single byte out on the I2C bus
*
* @param data data to write out on bus
*
* @returns
* '1' if an ACK was received,
* '0' otherwise
*/
int write(int data);
/** Creates a start condition on the I2C bus
*/
void start(void);
/** Creates a stop condition on the I2C bus
*/
void stop(void);
protected:
void aquire();
i2c_t _i2c;
static I2C *_owner;
int _hz;
};
} // namespace mbed
#endif
#endif

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targetlibs/libmbed/I2CSlave.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_I2C_SLAVE_H
#define MBED_I2C_SLAVE_H
#include "platform.h"
#if DEVICE_I2CSLAVE
#include "i2c_api.h"
namespace mbed {
/** An I2C Slave, used for communicating with an I2C Master device
*
* Example:
* @code
* // Simple I2C responder
* #include <mbed.h>
*
* I2CSlave slave(p9, p10);
*
* int main() {
* char buf[10];
* char msg[] = "Slave!";
*
* slave.address(0xA0);
* while (1) {
* int i = slave.receive();
* switch (i) {
* case I2CSlave::ReadAddressed:
* slave.write(msg, strlen(msg) + 1); // Includes null char
* break;
* case I2CSlave::WriteGeneral:
* slave.read(buf, 10);
* printf("Read G: %s\n", buf);
* break;
* case I2CSlave::WriteAddressed:
* slave.read(buf, 10);
* printf("Read A: %s\n", buf);
* break;
* }
* for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
* }
* }
* @endcode
*/
class I2CSlave {
public:
enum RxStatus {
NoData = 0,
ReadAddressed = 1,
WriteGeneral = 2,
WriteAddressed = 3
};
/** Create an I2C Slave interface, connected to the specified pins.
*
* @param sda I2C data line pin
* @param scl I2C clock line pin
*/
I2CSlave(PinName sda, PinName scl);
/** Set the frequency of the I2C interface
*
* @param hz The bus frequency in hertz
*/
void frequency(int hz);
/** Checks to see if this I2C Slave has been addressed.
*
* @returns
* A status indicating if the device has been addressed, and how
* - NoData - the slave has not been addressed
* - ReadAddressed - the master has requested a read from this slave
* - WriteAddressed - the master is writing to this slave
* - WriteGeneral - the master is writing to all slave
*/
int receive(void);
/** Read from an I2C master.
*
* @param data pointer to the byte array to read data in to
* @param length maximum number of bytes to read
*
* @returns
* 0 on success,
* non-0 otherwise
*/
int read(char *data, int length);
/** Read a single byte from an I2C master.
*
* @returns
* the byte read
*/
int read(void);
/** Write to an I2C master.
*
* @param data pointer to the byte array to be transmitted
* @param length the number of bytes to transmite
*
* @returns
* 0 on success,
* non-0 otherwise
*/
int write(const char *data, int length);
/** Write a single byte to an I2C master.
*
* @data the byte to write
*
* @returns
* '1' if an ACK was received,
* '0' otherwise
*/
int write(int data);
/** Sets the I2C slave address.
*
* @param address The address to set for the slave (ignoring the least
* signifcant bit). If set to 0, the slave will only respond to the
* general call address.
*/
void address(int address);
/** Reset the I2C slave back into the known ready receiving state.
*/
void stop(void);
protected:
i2c_t _i2c;
};
} // namespace mbed
#endif
#endif

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targetlibs/libmbed/InterruptIn.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_INTERRUPTIN_H
#define MBED_INTERRUPTIN_H
#include "platform.h"
#if DEVICE_INTERRUPTIN
#include "gpio_api.h"
#include "gpio_irq_api.h"
#include "FunctionPointer.h"
namespace mbed {
/** A digital interrupt input, used to call a function on a rising or falling edge
*
* Example:
* @code
* // Flash an LED while waiting for events
*
* #include "mbed.h"
*
* InterruptIn event(p16);
* DigitalOut led(LED1);
*
* void trigger() {
* printf("triggered!\n");
* }
*
* int main() {
* event.rise(&trigger);
* while(1) {
* led = !led;
* wait(0.25);
* }
* }
* @endcode
*/
class InterruptIn {
public:
/** Create an InterruptIn connected to the specified pin
*
* @param pin InterruptIn pin to connect to
* @param name (optional) A string to identify the object
*/
InterruptIn(PinName pin);
virtual ~InterruptIn();
int read();
#ifdef MBED_OPERATORS
operator int();
#endif
/** Attach a function to call when a rising edge occurs on the input
*
* @param fptr A pointer to a void function, or 0 to set as none
*/
void rise(void (*fptr)(void));
/** Attach a member function to call when a rising edge occurs on the input
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
*/
template<typename T>
void rise(T* tptr, void (T::*mptr)(void)) {
_rise.attach(tptr, mptr);
gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
}
/** Attach a function to call when a falling edge occurs on the input
*
* @param fptr A pointer to a void function, or 0 to set as none
*/
void fall(void (*fptr)(void));
/** Attach a member function to call when a falling edge occurs on the input
*
* @param tptr pointer to the object to call the member function on
* @param mptr pointer to the member function to be called
*/
template<typename T>
void fall(T* tptr, void (T::*mptr)(void)) {
_fall.attach(tptr, mptr);
gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
}
/** Set the input pin mode
*
* @param mode PullUp, PullDown, PullNone
*/
void mode(PinMode pull);
static void _irq_handler(uint32_t id, gpio_irq_event event);
protected:
gpio_t gpio;
gpio_irq_t gpio_irq;
FunctionPointer _rise;
FunctionPointer _fall;
};
} // namespace mbed
#endif
#endif

14
targetlibs/libmbed/KL25Z/ARM/MKL25Z4.sct
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LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x20000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 0x4000 - 0xC0 = 0x3F40
RW_IRAM1 0x1FFFF0C0 0x3F40 {
.ANY (+RW +ZI)
}
}

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targetlibs/libmbed/KL25Z/ARM/mbed.ar
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targetlibs/libmbed/KL25Z/MKL25Z4.h
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86
targetlibs/libmbed/KL25Z/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)UART0_BASE,
UART_1 = (int)UART1_BASE,
UART_2 = (int)UART2_BASE
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = (int)I2C0_BASE,
I2C_1 = (int)I2C1_BASE,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
} PWMName;
typedef enum {
ADC0_SE0 = 0,
ADC0_SE3 = 3,
ADC0_SE4b = 4,
ADC0_SE5b = 5,
ADC0_SE6b = 6,
ADC0_SE7b = 7,
ADC0_SE8 = 8,
ADC0_SE9 = 9,
ADC0_SE11 = 11,
ADC0_SE12 = 12,
ADC0_SE13 = 13,
ADC0_SE14 = 14,
ADC0_SE15 = 15,
ADC0_SE23 = 23
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = (int)SPI0_BASE,
SPI_1 = (int)SPI1_BASE,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

247
targetlibs/libmbed/KL25Z/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 12
typedef enum {
PTA0 = 0x0,
PTA1 = 0x4,
PTA2 = 0x8,
PTA3 = 0xc,
PTA4 = 0x10,
PTA5 = 0x14,
PTA6 = 0x18,
PTA7 = 0x1c,
PTA8 = 0x20,
PTA9 = 0x24,
PTA10 = 0x28,
PTA11 = 0x2c,
PTA12 = 0x30,
PTA13 = 0x34,
PTA14 = 0x38,
PTA15 = 0x3c,
PTA16 = 0x40,
PTA17 = 0x44,
PTA18 = 0x48,
PTA19 = 0x4c,
PTA20 = 0x50,
PTA21 = 0x54,
PTA22 = 0x58,
PTA23 = 0x5c,
PTA24 = 0x60,
PTA25 = 0x64,
PTA26 = 0x68,
PTA27 = 0x6c,
PTA28 = 0x70,
PTA29 = 0x74,
PTA30 = 0x78,
PTA31 = 0x7c,
PTB0 = 0x1000,
PTB1 = 0x1004,
PTB2 = 0x1008,
PTB3 = 0x100c,
PTB4 = 0x1010,
PTB5 = 0x1014,
PTB6 = 0x1018,
PTB7 = 0x101c,
PTB8 = 0x1020,
PTB9 = 0x1024,
PTB10 = 0x1028,
PTB11 = 0x102c,
PTB12 = 0x1030,
PTB13 = 0x1034,
PTB14 = 0x1038,
PTB15 = 0x103c,
PTB16 = 0x1040,
PTB17 = 0x1044,
PTB18 = 0x1048,
PTB19 = 0x104c,
PTB20 = 0x1050,
PTB21 = 0x1054,
PTB22 = 0x1058,
PTB23 = 0x105c,
PTB24 = 0x1060,
PTB25 = 0x1064,
PTB26 = 0x1068,
PTB27 = 0x106c,
PTB28 = 0x1070,
PTB29 = 0x1074,
PTB30 = 0x1078,
PTB31 = 0x107c,
PTC0 = 0x2000,
PTC1 = 0x2004,
PTC2 = 0x2008,
PTC3 = 0x200c,
PTC4 = 0x2010,
PTC5 = 0x2014,
PTC6 = 0x2018,
PTC7 = 0x201c,
PTC8 = 0x2020,
PTC9 = 0x2024,
PTC10 = 0x2028,
PTC11 = 0x202c,
PTC12 = 0x2030,
PTC13 = 0x2034,
PTC14 = 0x2038,
PTC15 = 0x203c,
PTC16 = 0x2040,
PTC17 = 0x2044,
PTC18 = 0x2048,
PTC19 = 0x204c,
PTC20 = 0x2050,
PTC21 = 0x2054,
PTC22 = 0x2058,
PTC23 = 0x205c,
PTC24 = 0x2060,
PTC25 = 0x2064,
PTC26 = 0x2068,
PTC27 = 0x206c,
PTC28 = 0x2070,
PTC29 = 0x2074,
PTC30 = 0x2078,
PTC31 = 0x207c,
PTD0 = 0x3000,
PTD1 = 0x3004,
PTD2 = 0x3008,
PTD3 = 0x300c,
PTD4 = 0x3010,
PTD5 = 0x3014,
PTD6 = 0x3018,
PTD7 = 0x301c,
PTD8 = 0x3020,
PTD9 = 0x3024,
PTD10 = 0x3028,
PTD11 = 0x302c,
PTD12 = 0x3030,
PTD13 = 0x3034,
PTD14 = 0x3038,
PTD15 = 0x303c,
PTD16 = 0x3040,
PTD17 = 0x3044,
PTD18 = 0x3048,
PTD19 = 0x304c,
PTD20 = 0x3050,
PTD21 = 0x3054,
PTD22 = 0x3058,
PTD23 = 0x305c,
PTD24 = 0x3060,
PTD25 = 0x3064,
PTD26 = 0x3068,
PTD27 = 0x306c,
PTD28 = 0x3070,
PTD29 = 0x3074,
PTD30 = 0x3078,
PTD31 = 0x307c,
PTE0 = 0x4000,
PTE1 = 0x4004,
PTE2 = 0x4008,
PTE3 = 0x400c,
PTE4 = 0x4010,
PTE5 = 0x4014,
PTE6 = 0x4018,
PTE7 = 0x401c,
PTE8 = 0x4020,
PTE9 = 0x4024,
PTE10 = 0x4028,
PTE11 = 0x402c,
PTE12 = 0x4030,
PTE13 = 0x4034,
PTE14 = 0x4038,
PTE15 = 0x403c,
PTE16 = 0x4040,
PTE17 = 0x4044,
PTE18 = 0x4048,
PTE19 = 0x404c,
PTE20 = 0x4050,
PTE21 = 0x4054,
PTE22 = 0x4058,
PTE23 = 0x405c,
PTE24 = 0x4060,
PTE25 = 0x4064,
PTE26 = 0x4068,
PTE27 = 0x406c,
PTE28 = 0x4070,
PTE29 = 0x4074,
PTE30 = 0x4078,
PTE31 = 0x407c,
LED_RED = PTB18,
LED_GREEN = PTB19,
LED_BLUE = PTD1,
// mbed original LED naming
LED1 = LED_BLUE,
LED2 = LED_GREEN,
LED3 = LED_RED,
LED4 = LED_RED,
// USB Pins
USBTX = PTA2,
USBRX = PTA1,
// Arduino Headers
D0 = PTA1,
D1 = PTA2,
D2 = PTD4,
D3 = PTA12,
D4 = PTA4,
D5 = PTA5,
D6 = PTC8,
D7 = PTC9,
D8 = PTA13,
D9 = PTD5,
D10 = PTD0,
D11 = PTD2,
D12 = PTD3,
D13 = PTD1,
D14 = PTE0,
D15 = PTE1,
A0 = PTB0,
A1 = PTB1,
A2 = PTB2,
A3 = PTB3,
A4 = PTC2,
A5 = PTC1,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 2,
PullUp = 3,
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

34
targetlibs/libmbed/KL25Z/PortNames.h
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@ -1,34 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
PortE = 4
} PortName;
#ifdef __cplusplus
}
#endif
#endif

13
targetlibs/libmbed/KL25Z/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MKL25Z4.h"
#include "cmsis_nvic.h"
#endif

23
targetlibs/libmbed/KL25Z/cmsis_nvic.h
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@ -1,23 +0,0 @@
/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

778
targetlibs/libmbed/KL25Z/core_cm0plus.h
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@ -1,778 +0,0 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.02
* @date 05. November 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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targetlibs/libmbed/KL25Z/core_cmFunc.h
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@ -1,616 +0,0 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.02
* @date 24. May 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

643
targetlibs/libmbed/KL25Z/core_cmInstr.h
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@ -1,643 +0,0 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.03
* @date 29. August 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

58
targetlibs/libmbed/KL25Z/device.h
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@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 1
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 1
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 1
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 24
#define DEVICE_SLEEP 0
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_ERROR_RED 1
#include "objects.h"
#endif

48
targetlibs/libmbed/KL25Z/gpio_object.h
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@ -1,48 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

75
targetlibs/libmbed/KL25Z/objects.h
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@ -1,75 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t port;
uint32_t pin;
uint32_t ch;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct pwmout_s {
__IO uint32_t *MOD;
__IO uint32_t *CNT;
__IO uint32_t *CnV;
};
struct serial_s {
UARTLP_Type *uart;
int index;
};
struct analogin_s {
ADCName adc;
};
struct dac_s {
DACName dac;
};
struct i2c_s {
I2C_Type *i2c;
};
struct spi_s {
SPI_Type *spi;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

84
targetlibs/libmbed/KL25Z/system_MKL25Z4.h
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@ -1,84 +0,0 @@
/*
** ###################################################################
** Processor: MKL25Z128VLK4
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL25RM, Rev.1, Jun 2012
** Version: rev. 1.1, 2012-06-21
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-13)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
**
** ###################################################################
*/
/**
* @file MKL25Z4
* @version 1.1
* @date 2012-06-21
* @brief Device specific configuration file for MKL25Z4 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MKL25Z4_H_
#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */

14
targetlibs/libmbed/LPC11U24/ARM/LPC11U24.sct
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@ -1,14 +0,0 @@
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0xF40
RW_IRAM1 0x100000C0 0xF40 {
.ANY (+RW +ZI)
}
}

BIN
targetlibs/libmbed/LPC11U24/ARM/mbed.ar
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670
targetlibs/libmbed/LPC11U24/LPC11Uxx.h
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/****************************************************************************************************//**
* @file LPC11Uxx.h
*
*
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
* default LPC11Uxx Device Series
*
* @version V0.1
* @date 21. March 2011
*
* @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
*
* from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
* created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
*
*******************************************************************************************************/
// ################################################################################
// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
// ################################################################################
/** @addtogroup NXP
* @{
*/
/** @addtogroup LPC11Uxx
* @{
*/
#ifndef __LPC11UXX_H__
#define __LPC11UXX_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/* Interrupt Number Definition */
typedef enum {
// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
FLEX_INT1_IRQn = 1,
FLEX_INT2_IRQn = 2,
FLEX_INT3_IRQn = 3,
FLEX_INT4_IRQn = 4,
FLEX_INT5_IRQn = 5,
FLEX_INT6_IRQn = 6,
FLEX_INT7_IRQn = 7,
GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
Reserved0_IRQn = 10, /*!< Reserved Interrupt */
Reserved1_IRQn = 11,
Reserved2_IRQn = 12,
Reserved3_IRQn = 13,
SSP1_IRQn = 14, /*!< SSP1 Interrupt */
I2C_IRQn = 15, /*!< I2C Interrupt */
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /*!< SSP0 Interrupt */
UART_IRQn = 21, /*!< UART Interrupt */
USB_IRQn = 22, /*!< USB IRQ Interrupt */
USB_FIQn = 23, /*!< USB FIQ Interrupt */
ADC_IRQn = 24, /*!< A/D Converter Interrupt */
WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
Reserved4_IRQn = 28, /*!< Reserved Interrupt */
Reserved5_IRQn = 29, /*!< Reserved Interrupt */
USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
Reserved6_IRQn = 31, /*!< Reserved Interrupt */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
/** @addtogroup Device_Peripheral_Registers
* @{
*/
// ------------------------------------------------------------------------------------------------
// ----- I2C -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
*/
typedef struct { /*!< (@ 0x40000000) I2C Structure */
__IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
__I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
__IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
__IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
__IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
__IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
__IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
__IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
__IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
__IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
__IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
__I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
union{
__IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
struct{
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
};
};
} LPC_I2C_Type;
// ------------------------------------------------------------------------------------------------
// ----- WWDT -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
*/
typedef struct { /*!< (@ 0x40004000) WWDT Structure */
__IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
__IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
__IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
__I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
__IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
__IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
__IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
} LPC_WWDT_Type;
// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
*/
typedef struct { /*!< (@ 0x40008000) USART Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
__O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
};
union {
__O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
__I uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
__I uint32_t RESERVED1;
__IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__IO uint32_t SYNCCTRL;
} LPC_USART_Type;
// ------------------------------------------------------------------------------------------------
// ----- Timer -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
*/
typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
__IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
__IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
__IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
__IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
__IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
__IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
union {
__IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
struct{
__IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
__IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
__IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
__IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
};
};
__IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
union{
__I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
struct{
__I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
__I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
__I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
__I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
};
};
__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
__IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
} LPC_CTxxBx_Type;
// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
*/
typedef struct { /*!< (@ 0x4001C000) ADC Structure */
__IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
__IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
__I uint32_t RESERVED0[1];
__IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
union{
__I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
struct{
__IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
__IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
__IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
__IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
__IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
__IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
__IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
__IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
};
};
__I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
} LPC_ADC_Type;
// ------------------------------------------------------------------------------------------------
// ----- PMU -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
*/
typedef struct { /*!< (@ 0x40038000) PMU Structure */
__IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
union{
__IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
struct{
__IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
__IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
__IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
__IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
};
};
} LPC_PMU_Type;
// ------------------------------------------------------------------------------------------------
// ----- FLASHCTRL -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
*/
typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
__I uint32_t RESERVED0[4];
__IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
__I uint32_t RESERVED1[3];
__IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
__IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
__I uint32_t RESERVED2[1];
__I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
__I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
__I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
__I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
__I uint32_t RESERVED3[1001];
__I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
__I uint32_t RESERVED4[1];
__IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
} LPC_FLASHCTRL_Type;
// ------------------------------------------------------------------------------------------------
// ----- SSP0/1 -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
*/
typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
__IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
__IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
__IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
__I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
} LPC_SSPx_Type;
// ------------------------------------------------------------------------------------------------
// ----- IOCONFIG -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
*/
typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
__IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
__IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
__IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
__IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
__IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
__IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
__IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
__IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
__IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
__IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
__IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
__IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
__IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
__IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
__IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
__IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
__IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
__IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
__IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
__IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
__IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
__IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
__IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
__IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
__IO uint32_t PIO1_0; /*!< Offset: 0x060 */
__IO uint32_t PIO1_1;
__IO uint32_t PIO1_2;
__IO uint32_t PIO1_3;
__IO uint32_t PIO1_4; /*!< Offset: 0x070 */
__IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
__IO uint32_t PIO1_6;
__IO uint32_t PIO1_7;
__IO uint32_t PIO1_8; /*!< Offset: 0x080 */
__IO uint32_t PIO1_9;
__IO uint32_t PIO1_10;
__IO uint32_t PIO1_11;
__IO uint32_t PIO1_12; /*!< Offset: 0x090 */
__IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
__IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
__IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
__IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
__IO uint32_t PIO1_17;
__IO uint32_t PIO1_18;
__IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
__IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
__IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
__IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
__IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
__IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
__IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
__IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
__IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
__IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
__IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
__IO uint32_t PIO1_30;
__IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
} LPC_IOCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- SYSCON -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
*/
typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
__IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
__IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
__IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
__I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
__IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
__I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
__I uint32_t RESERVED0[2];
__IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
__IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
__IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
__IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
__IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
__I uint32_t RESERVED3[8];
__IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
__IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
__IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
__I uint32_t RESERVED4[1];
__IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
__I uint32_t RESERVED5[4];
__IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
__IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
__IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
__I uint32_t RESERVED6[8];
__IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
__IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
__IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
__I uint32_t RESERVED7[5];
__IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
__IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
__IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
__I uint32_t RESERVED8[5];
__I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
__I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
__I uint32_t RESERVED9[18];
__IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
__IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
__I uint32_t RESERVED10[6];
__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
__IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
__IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
__IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
__I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
__I uint32_t RESERVED11[25];
__IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
__I uint32_t RESERVED12[3];
__IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
__I uint32_t RESERVED13[6];
__IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
__IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
__IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
__I uint32_t RESERVED14[110];
__I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
} LPC_SYSCON_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PIN_INT -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
*/
typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
} LPC_GPIO_PIN_INT_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_GROUP_INT0/1 -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
*/
typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
__IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
__I uint32_t RESERVED1[6];
__IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
} LPC_GPIO_GROUP_INTx_Type;
// ------------------------------------------------------------------------------------------------
// ----- USB -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
*/
typedef struct { /*!< (@ 0x40080000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
} LPC_USB_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO_PORT -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
*/
typedef struct {
union {
struct {
__IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
__IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
};
__IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
};
__I uint32_t RESERVED0[1008];
union {
struct {
__IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
__IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
};
__IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
};
uint32_t RESERVED1[960];
__IO uint32_t DIR[2]; /* 0x2000 */
uint32_t RESERVED2[30];
__IO uint32_t MASK[2]; /* 0x2080 */
uint32_t RESERVED3[30];
__IO uint32_t PIN[2]; /* 0x2100 */
uint32_t RESERVED4[30];
__IO uint32_t MPIN[2]; /* 0x2180 */
uint32_t RESERVED5[30];
__IO uint32_t SET[2]; /* 0x2200 */
uint32_t RESERVED6[30];
__O uint32_t CLR[2]; /* 0x2280 */
uint32_t RESERVED7[30];
__O uint32_t NOT[2]; /* 0x2300 */
} LPC_GPIO_Type;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C_BASE (0x40000000)
#define LPC_WWDT_BASE (0x40004000)
#define LPC_USART_BASE (0x40008000)
#define LPC_CT16B0_BASE (0x4000C000)
#define LPC_CT16B1_BASE (0x40010000)
#define LPC_CT32B0_BASE (0x40014000)
#define LPC_CT32B1_BASE (0x40018000)
#define LPC_ADC_BASE (0x4001C000)
#define LPC_PMU_BASE (0x40038000)
#define LPC_FLASHCTRL_BASE (0x4003C000)
#define LPC_SSP0_BASE (0x40040000)
#define LPC_SSP1_BASE (0x40058000)
#define LPC_IOCON_BASE (0x40044000)
#define LPC_SYSCON_BASE (0x40048000)
#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
#define LPC_USB_BASE (0x40080000)
#define LPC_GPIO_BASE (0x50000000)
// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------
#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group (null) */
/** @} */ /* End of group LPC11Uxx */
#ifdef __cplusplus
}
#endif
#endif // __LPC11UXX_H__

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targetlibs/libmbed/LPC11U24/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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targetlibs/libmbed/LPC11U24/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
p5 = P0_9,
p6 = P0_8,
p7 = P1_29,
p8 = P0_2,
p9 = P1_27,
p10 = P1_26,
p11 = P1_22,
p12 = P1_21,
p13 = P1_20,
p14 = P1_23,
p15 = P0_11,
p16 = P0_12,
p17 = P0_13,
p18 = P0_14,
p19 = P0_16,
p20 = P0_22,
p21 = P0_7,
p22 = P0_17,
p23 = P1_17,
p24 = P1_18,
p25 = P1_24,
p26 = P1_25,
p27 = P0_4,
p28 = P0_5,
p29 = P1_5,
p30 = P1_2,
p33 = P0_3,
p34 = P1_15,
p35 = P0_20,
p36 = P0_21,
// Other mbed Pin Names
LED1 = P1_8,
LED2 = P1_9,
LED3 = P1_10,
LED4 = P1_11,
USBTX = P0_19,
USBRX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targetlibs/libmbed/LPC11U24/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targetlibs/libmbed/LPC11U24/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC11Uxx.h"
#include "cmsis_nvic.h"
#endif

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targetlibs/libmbed/LPC11U24/cmsis_nvic.h
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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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targetlibs/libmbed/LPC11U24/core_cm0.h
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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.02
* @date 05. November 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

616
targetlibs/libmbed/LPC11U24/core_cmFunc.h
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@ -1,616 +0,0 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.02
* @date 24. May 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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targetlibs/libmbed/LPC11U24/core_cmInstr.h
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@ -1,643 +0,0 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.03
* @date 29. August 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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targetlibs/libmbed/LPC11U24/device.h
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@ -1,59 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 1
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 1
#define DEVICE_SEMIHOST 1
#define DEVICE_LOCALFILESYSTEM 1
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#define DEVICE_SLEEP 1
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_ERROR_PATTERN 1
#include "objects.h"
#endif

48
targetlibs/libmbed/LPC11U24/gpio_object.h
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@ -1,48 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

66
targetlibs/libmbed/LPC11U24/objects.h
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@ -1,66 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_mpin;
PortName port;
uint32_t mask;
};
struct pwmout_s {
PWMName pwm;
};
struct serial_s {
LPC_USART_Type *uart;
int index;
};
struct analogin_s {
ADCName adc;
};
struct i2c_s {
LPC_I2C_Type *i2c;
};
struct spi_s {
LPC_SSPx_Type *spi;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

82
targetlibs/libmbed/LPC11U24/power_api.h
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@ -1,82 +0,0 @@
/****************************************************************************
* $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
* Project: NXP LPC11Uxx software example
*
* Description:
* Power API Header File for NXP LPC11Uxx Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
****************************************************************************/
#ifndef __LPC11UXX_POWER_API_H__
#define __LPC11UXX_POWER_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#define PWRROMD_PRESENT
typedef struct _PWRD {
void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
void (*set_power)(unsigned int cmd[], unsigned int resp[]);
} PWRD;
typedef struct _ROM {
#ifdef USBROMD_PRESENT
const USB * pUSBD;
#else
const unsigned p_usbd;
#endif /* USBROMD_PRESENT */
const unsigned p_clib;
const unsigned p_cand;
#ifdef PWRROMD_PRESENT
const PWRD * pPWRD;
#else
const unsigned p_pwrd;
#endif /* PWRROMD_PRESENT */
const unsigned p_dev1;
const unsigned p_dev2;
const unsigned p_dev3;
const unsigned p_dev4;
} ROM;
//PLL setup related definitions
#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
//power setup elated definitions
#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
#define PARAM_CMD_SUCCESS 0 //power setting successfully found
#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
#define MAX_CLOCK_KHZ_PARAM 50000
#ifdef __cplusplus
}
#endif
#endif /* __LPC11UXX_POWER_API_H__ */

64
targetlibs/libmbed/LPC11U24/system_LPC11Uxx.h
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@ -1,64 +0,0 @@
/**************************************************************************//**
* @file system_LPC11Uxx.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
* for the NXP LPC11Uxx Device Series
* @version V1.10
* @date 24. November 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC11Uxx_H
#define __SYSTEM_LPC11Uxx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC11Uxx_H */

14
targetlibs/libmbed/LPC11U24/uARM/LPC11U24.sct
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@ -1,14 +0,0 @@
LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0xF40
RW_IRAM1 0x100000C0 0xF40 {
.ANY (+RW +ZI)
}
}

BIN
targetlibs/libmbed/LPC11U24/uARM/mbed.ar
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22
targetlibs/libmbed/LPC1768/ARM/LPC1768.sct
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@ -1,22 +0,0 @@
LR_IROM1 0x00000000 0x80000 { ; load region size_region
ER_IROM1 0x00000000 0x80000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
; 32KB - 0xC8 = 0x7F38
RW_IRAM1 0x100000C8 0x7F38 {
.ANY (+RW +ZI)
}
RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
.ANY (AHBSRAM0)
}
RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
.ANY (AHBSRAM1)
}
RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
.ANY (CANRAM)
}
}

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