diff --git a/.travis.yml b/.travis.yml index 5cfb731d9..497da976a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -17,7 +17,7 @@ before_install: - sudo apt-get update - sudo apt-get install libsdl1.2-dev gcc-arm-embedded - curl -Ls http://s3.voneicken.com/xtensa-lx106-elf-20160330.tgx | tar Jxf - - - curl -Ls http://s3.voneicken.com/esp_iot_sdk_v1.5.0.tgx | tar Jxf - + - curl -Ls http://s3.voneicken.com/esp_iot_sdk_v2.0.0.p1.tgx | tar Jxf - before_script: - arm-none-eabi-gcc --version @@ -39,10 +39,10 @@ compiler: env: global: - - RELEASE=1 + #- RELEASE=1 - TRAVIS=1 - V=0 - - ESP8266_SDK_ROOT=$TRAVIS_BUILD_DIR/esp_iot_sdk_v1.5.0 + - ESP8266_SDK_ROOT=$TRAVIS_BUILD_DIR/esp_iot_sdk_v2.0.0.p1 - PATH=$PATH:$TRAVIS_BUILD_DIR/xtensa-lx106-elf/bin/ matrix: - ESP8266_BOARD=1 diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 0ad56db99..1425cc4a1 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,35 +1,78 @@ Contributing -=========== +============= Thanks for thinking about contributing to Espruino! Anything you can add is hugely appreciated, but please can you follow a few simple rules: -* Keep the same coding style (See **Coding Style** below) + +Support / Bugs +-------------- + +First, please try and check that your problem hasn't [already been found](https://github.com/espruino/Espruino/issues) or [covered on our forum](http://www.espruino.com/Forum). + +[Submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them: a minimal test case, and an actual and expected result. If you can't come up with these, please [post on the forum](http://www.espruino.com/Forum) first as it may just be something in your code that we can help out with. + +Work on Espruino is supported by [sales of our boards](http://www.espruino.com/Order). + +**If your board isn't made by us but came pre-installed with Espruino then you should contact the manufacturers.** + +We try and support users of the boards we sell, but if you bought a non-official board your issue may not get addressed. In this case, please consider [donating](http://www.espruino.com/Download) to help cover the time it takes to fix problems (even so, we can't guarantee to fix every problem). + + +Documentation +------------- + +Improvements to Documentation are amazingly helpful, and are very rare so hugely appreciated. + +### Functions/Variables + +If you want to change something in a [built-in function's documentation](http://www.espruino.com/Reference), look at the heading for the function on that page and there will be a right-arrow (⇒). + +If you click on that it will bring you to the area of Espruino's source code where the function *and the documentation for it* are stored. You can then edit the documentation in that file (above the function) on GitHub and issue a pull request - it's in Markdown format. + +### Tutorials + +Please [see here](http://www.espruino.com/Writing+Tutorials) + +### Other + +If there's something specific to an area of the Espruino interpreter *that can't be put in a source file*, please create a Markdown (`.md`) file in the relevant area, and make sure you link to it from other relevant files so it can be found. + + +Contributing Code +----------------- + +### Modules + +Please [see here](http://www.espruino.com/Writing+Modules) + +### Espruino code + +* Please keep the same coding style (See **Coding Style** below) +* Keep the minimum amount of changes in each pull request/commit (this really helps with debugging later on) +* Try not to commit huge whitespace/refactoring changes along with your fix +* Avoid adding newlines, spaces, refactoring everything or renaming things to your own personal style (some things really could do with renaming, but please check first or we may reject your pull request) * Ensure that you are not contributing someone else's code, and that you are willing to add your code under Espruino's MPL Licence * Make sure that what you do doesn't break the Espruino board or the other boards we build for. We can't check all the boards for every commit, so if you break something you'll annoy a whole bunch of people. * Be aware that Espruino is designed for Microcontrollers - with very low amounts of flash and memory. Both are at a premium so don't statically allocate variables or do other stuff that will use up RAM. -* Avoid randomly adding newlines, spaces, refactoring everything or renaming things to your own personal style (some things really could do with renaming, but please check first or we may reject your pull request) * Don't add a whole bunch of indirection/abstraction for the sake of it - it'll probably just use of more of our precious memory. * If you add a new API, try and make it familiar to Arduino/JavaScript users. +* Please [RUN THE TESTS](tests/README.md) before and after your changes to check that there are no regressions +* Finally, please issue us a pull request to [www.github.com/espruino](https://www.github.com/espruino/Espruino) via GitHub. It's way easier for us to incorporate, give credit, and track changes that way. + Target Areas ----------- We'll keep the outstanding issues in [GitHub's issue list](https://github.com/espruino/Espruino/issues), but general stuff that would really help us is: -* Tests. If something doesn't work, please make a test for it. Even if you don't fix it it'll help others greatly. Bonus points if it's in a pull request :) -* Documentation. Improving the documentation (either the EspruinoDocs project, source code, the auto-generated reference, or the Markdown files in this project) would be fantastic. -* Duplication. If the same code is used for multiple platforms, try and make sure it's shared, not duplicated. -* Remove hard-coded stuff. Some things are still hard-coded with ifdefs for each board - we want all that stuff to be generated from `build_platform_info.py` using the board definition file. -* Speed. There are a few areas this could be improved - but please benchmark what you're doing both before and afterwards on the Espruino board to check that what you've done helps. -* Memory Usage. Both RAM and Flash are at a premium. Ways of reducing this (including stack usage) and making usage more efficient are really appreciated. -* JavaScript compliance (without affecting speed or memory usage too much). +* **Tests** If something doesn't work, please make a test for it. Even if you don't fix it it'll help others greatly. Bonus points if it's in a pull request :) +* **Documentation** Improving the documentation (either the [EspruinoDocs](https://github.com/espruino/EspruinoDocs) project, source code, the auto-generated reference, or the Markdown files in this project) would be fantastic. +* **Duplication** If the same code is used for multiple platforms, try and make sure it's shared, not duplicated. +* **Remove hard-coded stuff** Some things are still hard-coded with ifdefs for each board - we want all that stuff to be generated from `build_platform_info.py` using the board definition file. +* **Speed** There are a few areas this could be improved - but please benchmark what you're doing both before and afterwards on the Espruino board to check that what you've done helps. +* **Memory Usage** Both RAM and Flash are at a premium. Ways of reducing this (including stack usage) and making usage more efficient are really appreciated. +* **JavaScript compliance** - without affecting speed or memory usage too much -Contributing ------------ - -* Please [RUN THE TESTS](tests/README.md) to check that there are no regressions -* Issue us a pull request to [www.github.com/espruino](https://www.github.com/espruino/Espruino) via GitHub -* Please keep each request small (just include one fix per request) Coding Style ----------- @@ -42,6 +85,9 @@ The rough coding style is as follows, but you should get a good idea from the co * No Tabs used, only spaces * Use `bool` for booleans - not `int` * ```//``` comments for single lines, ```/* ... */``` for multiple lines -* Half-hearted Doxygen compatibility: use ```///<``` for function declaration documentation (if on same line), and ```/** ... */``` if doing it right before a function +* Half-hearted Doxygen compatibility: use ```///<``` for function/variable declaration documentation (if on same line), and ```/** ... */``` if doing it right before a function +* If you're adding comments to a function, make sure they're in the header file, and if you are going to add comments in the source, make sure the two match. +* Do not add `setFooBar // This sets the Foo to Bar` style comments to functions/variables. Only add comments if they *add something that is not obvious from the declaration itself* * Use new lines in code sparingly (only where it really makes sense) + diff --git a/ChangeLog b/ChangeLog index 1b01ffbb0..b920b2851 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,19 @@ + 1v88 : jshSetEventCallback callbacks now get an argument with the channel number + Tab complete now offers a much better set of completions (fix #926) + Fix emitting of events with long names (fix #906) + Ensure 'af_opendrain' pin mode gets remembered when saving (fix #890) + Add second Promise.thenm argument (fix #869) + Fix 'chained' promises (fix #894) + Fixed memory leak when automatically converting a simple object to a String + Added ES6 Template Literals + Initial commit of ES6 arrow functions + Add 'opendrain_pullup' pinMode (including emulation on STM32F1) + Make OneWire use opendrain_pullup (no resistor needed for short runs now) + Add Software I2C (with opendrain_pullup) (ref #549, fix #29) + Cope with new escape codes for home and end on Ubuntu 16.04 (27,91,70/72) + Tweak VGA output back porch to 2ms (so leftmost pixels always on screen) + Fix regression with 2 concurrent waveforms on different pins (fix #930) + 1v87 : Add support for compiling with float-abi=hard (even if it doesn't give us real-world benefits) Add shortcut for quick execution of common call types Fix BBC micro:bit save() regression from 1v86 diff --git a/Makefile b/Makefile index 5cc6137a4..ab58f99d2 100755 --- a/Makefile +++ b/Makefile @@ -37,7 +37,6 @@ # RASPBERRYPI=1 # BEAGLEBONE=1 # ARIETTA=1 -# LPC1768=1 # beta # LCTECH_STM32F103RBT6=1 # LC Technology STM32F103RBT6 Ebay boards # ARMINARM=1 # NUCLEOF401RE=1 @@ -502,15 +501,6 @@ USE_CRYPTO=1 USE_NFC=1 USE_CUSTOM_BOOTLOADER=1 -else ifdef LPC1768 -EMBEDDED=1 -MBED=1 -BOARD=LPC1768 -MBED_GCC_CS_DIR=$(ROOT)/targetlibs/libmbed/LPC1768/GCC_CS -PRECOMPILED_OBJS+=$(MBED_GCC_CS_DIR)/sys.o $(MBED_GCC_CS_DIR)/cmsis_nvic.o $(MBED_GCC_CS_DIR)/system_LPC17xx.o $(MBED_GCC_CS_DIR)/core_cm3.o $(MBED_GCC_CS_DIR)/startup_LPC17xx.o -LIBS+=-L$(MBED_GCC_CS_DIR) -lmbed -OPTIMIZEFLAGS+=-O3 - else ifdef ECU # Gordon's car ECU (extremely beta!) USE_TRIGGER=1 @@ -568,19 +558,19 @@ else ifdef ESP8266_BOARD EMBEDDED=1 USE_NET=1 USE_TELNET=1 -USE_GRAPHICS=1 +#USE_GRAPHICS=1 USE_CRYPTO=1 BOARD=ESP8266_BOARD # Enable link-time optimisations (inlining across files), use -Os 'cause else we end up with # too large a firmware (-Os is -O2 without optimizations that increase code size) ifndef DISABLE_LTO -OPTIMIZEFLAGS+=-Os -std=gnu11 -fgnu89-inline -fno-fat-lto-objects -Wl,--allow-multiple-definition +OPTIMIZEFLAGS+=-Os -g -std=gnu11 -fgnu89-inline -fno-fat-lto-objects -Wl,--allow-multiple-definition #OPTIMIZEFLAGS+=-DLINK_TIME_OPTIMISATION # this actually slows things down! else # DISABLE_LTO is necessary in order to analyze static string sizes (see: topstring makefile target) OPTIMIZEFLAGS+=-Os -std=gnu11 -fgnu89-inline -Wl,--allow-multiple-definition endif -ESP_FLASH_MAX ?= 491520 # max bin file: 480KB +ESP_FLASH_MAX ?= 479232 # max bin file: 468KB ifdef FLASH_4MB ESP_FLASH_SIZE ?= 4 # 4->4MB (512KB+512KB) @@ -809,6 +799,7 @@ src/jspin.c \ src/jsinteractive.c \ src/jsdevices.c \ src/jstimer.c \ +src/jsi2c.c \ src/jsspi.c \ src/jshardware_common.c \ $(WRAPPERFILE) @@ -1387,82 +1378,6 @@ ifdef USE_NFC PRECOMPILED_OBJS += $(NRF5X_SDK_PATH)/components/nfc/t2t_lib/nfc_t2t_lib_gcc.a endif -ifeq ($(FAMILY), EFM32GG) - - EFM32=1 - - ARCHFLAGS += -mcpu=cortex-m3 -mthumb - - GECKO_SDK_PATH=$(ROOT)/targetlibs/Gecko_SDK - - ARM = 1 - ARM_HAS_OWN_CMSIS = 1 - INCLUDE += -I$(GECKO_SDK_PATH)/cmsis/Include - - LINKER_FILE = $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/efm32gg.ld - - INCLUDE += -I$(ROOT)/targets/efm32 - SOURCES += \ - targets/efm32/main.c \ - targets/efm32/jshardware.c - - INCLUDE += -I$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Include - INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/inc -# INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/ustimer/inc - INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/rtcdrv/inc - INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/nvm/inc - INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/common/inc - INCLUDE += -I$(GECKO_SDK_PATH)/emlib/inc - - TARGETSOURCES += \ - $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/startup_efm32gg.c \ - $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c \ - $(GECKO_SDK_PATH)/emlib/src/em_gpio.c \ - $(GECKO_SDK_PATH)/emlib/src/em_cmu.c \ - $(GECKO_SDK_PATH)/emlib/src/em_assert.c \ - $(GECKO_SDK_PATH)/emlib/src/em_emu.c \ - $(GECKO_SDK_PATH)/emlib/src/em_msc.c \ - $(GECKO_SDK_PATH)/emlib/src/em_rtc.c \ - $(GECKO_SDK_PATH)/emlib/src/em_int.c \ - $(GECKO_SDK_PATH)/emlib/src/em_system.c \ - $(GECKO_SDK_PATH)/emlib/src/em_timer.c \ - $(GECKO_SDK_PATH)/emlib/src/em_usart.c \ - $(GECKO_SDK_PATH)/emdrv/gpiointerrupt/src/gpiointerrupt.c \ - $(GECKO_SDK_PATH)/emdrv/rtcdrv/src/rtcdriver.c \ - $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c -# $(GECKO_SDK_PATH)/emdrv/ustimer/src/ustimer.c - - # $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm.c \ - # $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_acmp.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_adc.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_aes.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_burtc.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_crc.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_cryotimer.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_crypto.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_dac.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_dbg.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_dma.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_ebi.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_i2c.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_idac.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_lcd.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_ldma.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_lesense.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_letimer.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_leuart.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_mpu.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_opamp.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_pcnt.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_prs.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_rmu.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_rtcc.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_vcmp.c \ - # $(GECKO_SDK_PATH)/emlib/src/em_wdog.c - -endif #FAMILY == EFM32 - ifdef NRF5X # Just try and get rid of the compile warnings. CFLAGS += -Wno-sign-conversion -Wno-conversion -Wno-unused-parameter -fomit-frame-pointer #this is for device manager in nordic sdk @@ -1606,6 +1521,84 @@ ifdef NRF5X endif #NRF5X + +ifeq ($(FAMILY), EFM32GG) + + EFM32=1 + + ARCHFLAGS += -mcpu=cortex-m3 -mthumb + + GECKO_SDK_PATH=$(ROOT)/targetlibs/Gecko_SDK + + ARM = 1 + ARM_HAS_OWN_CMSIS = 1 + INCLUDE += -I$(GECKO_SDK_PATH)/cmsis/Include + + LINKER_FILE = $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/efm32gg.ld + + INCLUDE += -I$(ROOT)/targets/efm32 + SOURCES += \ + targets/efm32/main.c \ + targets/efm32/jshardware.c + + INCLUDE += -I$(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Include + INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/gpiointerrupt/inc +# INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/ustimer/inc + INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/rtcdrv/inc + INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/nvm/inc + INCLUDE += -I$(GECKO_SDK_PATH)/emdrv/common/inc + INCLUDE += -I$(GECKO_SDK_PATH)/emlib/inc + + TARGETSOURCES += \ + $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/GCC/startup_efm32gg.c \ + $(GECKO_SDK_PATH)/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c \ + $(GECKO_SDK_PATH)/emlib/src/em_gpio.c \ + $(GECKO_SDK_PATH)/emlib/src/em_cmu.c \ + $(GECKO_SDK_PATH)/emlib/src/em_assert.c \ + $(GECKO_SDK_PATH)/emlib/src/em_emu.c \ + $(GECKO_SDK_PATH)/emlib/src/em_msc.c \ + $(GECKO_SDK_PATH)/emlib/src/em_rtc.c \ + $(GECKO_SDK_PATH)/emlib/src/em_int.c \ + $(GECKO_SDK_PATH)/emlib/src/em_system.c \ + $(GECKO_SDK_PATH)/emlib/src/em_timer.c \ + $(GECKO_SDK_PATH)/emlib/src/em_usart.c \ + $(GECKO_SDK_PATH)/emdrv/gpiointerrupt/src/gpiointerrupt.c \ + $(GECKO_SDK_PATH)/emdrv/rtcdrv/src/rtcdriver.c \ + $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c +# $(GECKO_SDK_PATH)/emdrv/ustimer/src/ustimer.c + + # $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm.c \ + # $(GECKO_SDK_PATH)/emdrv/nvm/src/nvm_hal.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_acmp.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_adc.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_aes.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_burtc.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_crc.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_cryotimer.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_crypto.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_dac.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_dbg.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_dma.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_ebi.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_i2c.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_idac.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_lcd.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_ldma.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_lesense.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_letimer.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_leuart.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_mpu.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_opamp.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_pcnt.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_prs.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_rmu.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_rtcc.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_vcmp.c \ + # $(GECKO_SDK_PATH)/emlib/src/em_wdog.c + +endif #FAMILY == EFM32 + + ifeq ($(FAMILY),ESP8266) # move os_printf strings into flash to save RAM space DEFINES += -DUSE_OPTIMIZE_PRINTF @@ -1619,17 +1612,6 @@ CFLAGS+= -fno-builtin \ -Wl,EL -Wl,--gc-sections -nostdlib -mlongcalls -mtext-section-literals endif - -ifdef MBED -ARCHFLAGS += -mcpu=cortex-m3 -mthumb -ARM=1 -INCLUDE+=-I$(ROOT)/targetlibs/libmbed -I$(ROOT)/targetlibs/libmbed/$(CHIP) -I$(ROOT)/targetlibs/libmbed/$(CHIP)/GCC_CS -DEFINES += -DMBED -INCLUDE += -I$(ROOT)/targetlibs/mbed -SOURCES += targets/mbed/main.c -CPPSOURCES += targets/mbed/jshardware.cpp -endif - ifdef ARM ifndef LINKER_FILE # nRF5x targets define their own linker file. @@ -1936,7 +1918,7 @@ PARTIAL = espruino_esp8266_partial.o LD_SCRIPT1 = ./targets/esp8266/eagle.app.v6.new.1024.app1.ld LD_SCRIPT2 = ./targets/esp8266/eagle.app.v6.new.1024.app2.ld APPGEN_TOOL = $(ESP8266_SDK_ROOT)/tools/gen_appbin.py -BOOTLOADER = "$(ESP8266_SDK_ROOT)/bin/boot_v1.4(b1).bin" +BOOTLOADER = $(ESP8266_SDK_ROOT)/bin/boot_v1.6.bin BLANK = $(ESP8266_SDK_ROOT)/bin/blank.bin INIT_DATA = $(ESP8266_SDK_ROOT)/bin/esp_init_data_default.bin @@ -1989,7 +1971,7 @@ $(USER2_BIN): $(USER2_ELF) $(USER1_BIN) $(Q)$(OBJCOPY) --only-section .data -O binary $(USER2_ELF) eagle.app.v6.data.bin $(Q)$(OBJCOPY) --only-section .rodata -O binary $(USER2_ELF) eagle.app.v6.rodata.bin $(Q)$(OBJCOPY) --only-section .irom0.text -O binary $(USER2_ELF) eagle.app.v6.irom0text.bin - $(Q)COMPILE=gcc python $(APPGEN_TOOL) $(USER2_ELF) 2 $(ESP_FLASH_MODE) $(ESP_FLASH_FREQ_DIV) $(ESP_FLASH_SIZE) 0 >/dev/null + $(Q)COMPILE=gcc python $(APPGEN_TOOL) $(USER2_ELF) 2 $(ESP_FLASH_MODE) $(ESP_FLASH_FREQ_DIV) $(ESP_FLASH_SIZE) 1 >/dev/null $(Q) rm -f eagle.app.v6.*.bin $(Q) mv eagle.app.flash.bin $@ @@ -2167,7 +2149,7 @@ endif clean: @echo Cleaning targets - $(Q)find . -name \*.o | grep -v libmbed | grep -v arm-bcm2708 | xargs rm -f + $(Q)find . -name \*.o | grep -v arm-bcm2708 | xargs rm -f $(Q)rm -f $(ROOT)/gen/*.c $(ROOT)/gen/*.h $(ROOT)/gen/*.ld $(Q)rm -f $(PROJ_NAME).elf $(Q)rm -f $(PROJ_NAME).hex diff --git a/README.md b/README.md index 8da094ad3..ef6e3b2e7 100644 --- a/README.md +++ b/README.md @@ -13,9 +13,9 @@ http://www.espruino.com           [ About ----- -Espruino is a JavaScript interpreter for microcontrollers. It is designed to fit into devices with as little as 128kB Flash and 8kB RAM. +Espruino is a JavaScript interpreter for microcontrollers. It is designed for devices with as little as 128kB Flash and 8kB RAM. -Please support Espruino by [ordering one of our official boards](http://www.espruino.com/Order). +Please support Espruino by [ordering one of our official boards](http://www.espruino.com/Order) or [donating](http://www.espruino.com/Download) Documentation @@ -32,7 +32,7 @@ Builds for the [Espruino Board](http://www.espruino.com/EspruinoBoard) and [Pico Other documentation of use is: * [The Forum](http://forum.espruino.com/) -* [FAQ](http://www.espruino.com//FAQ) +* [FAQ](http://www.espruino.com/FAQ) * [Troubleshooting](http://www.espruino.com/Troubleshooting) * [Performance Notes](http://www.espruino.com/Performance) * [Implementation Notes](http://www.espruino.com/Internals) @@ -42,21 +42,27 @@ Other documentation of use is: * [Hardware Debugging Notes](http://www.espruino.com/AdvancedDebug) +Support / Bugs +-------------- + +First, please try and check that your problem hasn't [already been found](https://github.com/espruino/Espruino/issues) or [covered on our forum](http://www.espruino.com/Forum). + +[Submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them: a **small** test case (not your whole program), and an actual and expected result. If you can't come up with these, please [post on the forum](http://www.espruino.com/Forum) first as it may just be something in your code that we can help out with. + +Work on Espruino is supported by [sales of our boards](http://www.espruino.com/Order). + +**If your board isn't made by us but came pre-installed with Espruino then you should contact the manufacturers.** + +We try and support users of the boards we sell, but if you bought a non-official board your issue may not get addressed. In this case, please consider [donating](http://www.espruino.com/Download) to help cover the time it takes to fix problems (even so, we can't guarantee to fix every problem). + + License ------- Please see the [LICENSE](LICENSE) file -Found a Bug? ------------- - -Please check that it hasn't [already been found](https://github.com/espruino/Espruino/issues) or [been covered on our forum](http://www.espruino.com/Forum) - -Please [submit bugs](https://github.com/espruino/Espruino/issues) with clear steps to reproduce them (ideally with a test case for the ```tests``` directory). Please be aware that we're very busy, so if you report something (especially if it doesn't contain a test or a pull request) it may not be fixed for quite some time. - - -Building +Building -------- Check out [the page on building Espruino](README_Building.md) @@ -95,7 +101,6 @@ If you are a board manufacturer interested in getting your board officially supp * Carambola - WORKING - GPIO via filesystem (no I2C) * Raspberry Pi - WORKING - GPIO via filesystem or wiringPi (no I2C) * Sony SmartWatch - NOT WORKING - USB VCP support for F2 still needed -* MBed platforms - have not worked for a while - full hardware wrapper still required * LC-TECH STM32F103RBT6 - WORKING, but with some issues (LED inverted logic, BTN needs pullup to work) * [ST NUCLEO-F401RE](http://www.espruino.com/ReferenceNUCLEOF401RE) - WORKING * ST NUCLEO-F411RE - WORKING @@ -108,7 +113,7 @@ If you are a board manufacturer interested in getting your board officially supp Modification ------------ -**Check out [the documentation on the build process](README_BuildProcess.md) first** - this should +**Check out [the documentation on the build process](README_BuildProcess.md) first** - this should clear up a lot of potential questions about the Espruino architecture. Please see [CONTRIBUTING.md](CONTRIBUTING.md) for some hints about code style/etc. @@ -157,4 +162,3 @@ so because we make money from the sales of Espruino boards. If your users reques support from us then we have absolutely no obligation to help them. However, we'll be a lot more motivated if you're actively helping to improve Espruino for all its users (not just your own). - diff --git a/boards/ESP8266_BOARD.py b/boards/ESP8266_BOARD.py index 5a64c6c5e..831f8a13a 100644 --- a/boards/ESP8266_BOARD.py +++ b/boards/ESP8266_BOARD.py @@ -36,7 +36,7 @@ chip = { 'package' : "", 'ram' : 80, 'flash' : 0, - 'speed' : 80, + 'speed' : 160, 'usart' : 2, 'spi' : 1, 'i2c' : 1, @@ -46,7 +46,7 @@ chip = { 'address' : 0x78000, 'page_size' : 4096, 'pages' : 3, - 'flash_available' : 480, # firmware can be up to this size + 'flash_available' : 468, # firmware can be up to this size }, }; devices = { diff --git a/boards/ESPRUINOWIFI.py b/boards/ESPRUINOWIFI.py index 91b06089e..655b815b8 100644 --- a/boards/ESPRUINOWIFI.py +++ b/boards/ESPRUINOWIFI.py @@ -96,6 +96,8 @@ board = { 'left2' : ['A10','A8'], '_notes' : { + 'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole(true)` to avoid", + 'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole(true)` to avoid", 'A2' : 'ESP8266 RX', 'A3' : 'ESP8266 TX', 'A15' : 'ESP8266 CTS', # ESP8266 Clear to send (when enabled with AT+UART_DEF) diff --git a/boards/LPC1768.py b/boards/LPC1768.py deleted file mode 100644 index ea4da0470..000000000 --- a/boards/LPC1768.py +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/false -# This file is part of Espruino, a JavaScript interpreter for Microcontrollers -# -# Copyright (C) 2013 Gordon Williams -# -# This Source Code Form is subject to the terms of the Mozilla Public -# License, v. 2.0. If a copy of the MPL was not distributed with this -# file, You can obtain one at http://mozilla.org/MPL/2.0/. -# -# ---------------------------------------------------------------------------------------- -# This file contains information for a specific board - the available pins, and where LEDs, -# Buttons, and other in-built peripherals are. It is used to build documentation as well -# as various source and header files for Espruino. -# ---------------------------------------------------------------------------------------- - -import pinutils; -# placeholder -info = { - 'name' : "MBed LPC1768", - 'link' : [ "http://www.espruino.com/kick" ], - 'variables' : 2000, #? - 'binary_name' : 'espruino_%v_lpc1768.bin', - 'build' : { - 'defines' : [ - ] - } -}; -chip = { - 'part' : "LPC1768", - 'family' : "LPC1768", -# 'package' : "LQFP64", - 'ram' : 32, - 'flash' : 512, - 'speed' : 96, - 'usart' : 3, - 'spi' : 2, - 'i2c' : 2, - 'adc' : 6, - 'dac' : 0 -}; - -devices = { -}; - - -def get_pins(): - return [] diff --git a/boards/PICO_R1_3.py b/boards/PICO_R1_3.py index d8ce3363d..7bfba216a 100644 --- a/boards/PICO_R1_3.py +++ b/boards/PICO_R1_3.py @@ -89,8 +89,8 @@ board = { 'top2' : ['VBAT','3.3','GND'], 'right' : ['A4', 'A3', 'A2', 'A1', 'A0', 'A10', 'B9', 'B8'], '_notes' : { - 'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole()` to avoid", - 'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole()` to avoid", + 'B6' : "Serial Console TX when USB disconnected, use `USB.setConsole(true)` to avoid", + 'B7' : "Serial Console RX when USB disconnected, use `USB.setConsole(true)` to avoid", 'A9' : "Connected directly to USB 5V", 'A13' : "Accessible on row of gold SMD pads on underside", 'A14' : "Accessible on row of gold SMD pads on underside", diff --git a/libs/bluetooth/jswrap_bluetooth.c b/libs/bluetooth/jswrap_bluetooth.c index 426f57aa4..8591ae72b 100644 --- a/libs/bluetooth/jswrap_bluetooth.c +++ b/libs/bluetooth/jswrap_bluetooth.c @@ -80,6 +80,7 @@ bool nfcEnabled = false; #define FIRST_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(5000, APP_TIMER_PRESCALER) /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */ #define NEXT_CONN_PARAMS_UPDATE_DELAY APP_TIMER_TICKS(30000, APP_TIMER_PRESCALER) /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */ #define MAX_CONN_PARAMS_UPDATE_COUNT 3 /**< Number of attempts before giving up the connection parameter negotiation. */ +#define APP_CFG_CHAR_MAX_LEN 20 /**< Size of the characteristic value being notified (in bytes). */ #ifdef USE_BOOTLOADER #define SEC_PARAM_BOND 1 /**< Perform bonding. */ @@ -256,10 +257,8 @@ void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info) { } void advertising_start(void) { - uint32_t err_code = 0; - if (bleStatus & BLE_IS_ADVERTISING) return; - // Actually start advertising + ble_gap_adv_params_t adv_params; memset(&adv_params, 0, sizeof(adv_params)); adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND; @@ -268,8 +267,7 @@ void advertising_start(void) { adv_params.timeout = APP_ADV_TIMEOUT_IN_SECONDS; adv_params.interval = advertising_interval; - err_code = sd_ble_gap_adv_start(&adv_params); - // APP_ERROR_CHECK(err_code); // don't bother checking + sd_ble_gap_adv_start(&adv_params); bleStatus |= BLE_IS_ADVERTISING; } @@ -693,6 +691,7 @@ static void on_ble_evt(ble_evt_t * p_ble_evt) switch (p_ble_evt->header.evt_id) { case BLE_GAP_EVT_TIMEOUT: // the timeout for sd_ble_gap_adv_start expired - kick it off again + bleStatus &= ~BLE_IS_ADVERTISING; // we still think we're advertising, but we stopped advertising_start(); break; @@ -1126,7 +1125,6 @@ void jswrap_nrf_bluetooth_sleep(void) { // Stop advertising if (bleStatus & BLE_IS_ADVERTISING) advertising_stop(); - NRF_RADIO->TASKS_DISABLE = (1UL); } /*JSON{ @@ -1138,7 +1136,6 @@ void jswrap_nrf_bluetooth_sleep(void) { Enable Bluetooth communications (they are enabled by default) */ void jswrap_nrf_bluetooth_wake(void) { - // NRF_RADIO->TASKS_DISABLE = (0UL); // BUG: This was causing a hardfault. advertising_start(); } @@ -1365,6 +1362,7 @@ NRF.setServices({ readable : true, // optional, default is false writable : true, // optional, default is false notify : true, // optional, default is false + indicate : true, // optional, default is false onWrite : function(evt) { // optional console.log("Got ", evt.data); } @@ -1429,6 +1427,8 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) { char_md.char_props.broadcast = 1; if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "notify", 0))) char_md.char_props.notify = 1; + if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "indicate", 0))) + char_md.char_props.indicate = 1; if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "readable", 0))) char_md.char_props.read = 1; if (jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "writable", 0))) { @@ -1490,19 +1490,6 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) { } jsvUnLock(charVar); - /* We'd update the characteristic with: - - memset(&hvx_params, 0, sizeof(hvx_params)); - hvx_params.handle = characteristic_handle.value_handle; - hvx_params.p_data = p_string; - hvx_params.p_len = &length; - hvx_params.type = BLE_GATT_HVX_NOTIFICATION; - return sd_ble_gatts_hvx(p_nus->conn_handle, &hvx_params); - - Maybe we could find the handle out based on characteristic UUID, rather than having - to store it? - - */ jsvObjectIteratorNext(&serviceit); } @@ -1520,6 +1507,181 @@ void jswrap_nrf_bluetooth_setServices(JsVar *data) { } } +/*JSON{ + "type" : "staticmethod", + "class" : "NRF", + "name" : "updateServices", + "generate" : "jswrap_nrf_bluetooth_updateServices", + "params" : [ + ["data","JsVar","The service (and characteristics) to update"] + ] +} + +Update values for the services and characteristics Espruino advertises. +Only services and characteristics previously declared using `setServices` are affected. + +To update the '0xABCD' characteristic in the '0xBCDE' service: +``` +NRF.updateServices({ + 0xBCDE : { + 0xABCD : { + value : "World" + } + } +}); +``` + +To notify connected clients of a change to the '0xABCD' characteristic in the '0xBCDE' service: +``` +NRF.updateServices({ + 0xBCDE : { + 0xABCD : { + value : "World", + notify: true + } + } +}); +``` +This only works if the characteristic was created with `notify: true` using `setServices`, +otherwise the characteristic will be updated but no notification will be sent. + +To indicate (i.e. notify with ACK) connected clients of a change to the '0xABCD' characteristic in the '0xBCDE' service: +``` +NRF.updateServices({ + 0xBCDE : { + 0xABCD : { + value : "World", + indicate: true + } + } +}); +``` +This only works if the characteristic was created with `indicate: true` using `setServices`, +otherwise the characteristic will be updated but no notification will be sent. + +**Note:** See `setServices` for more information +*/ +void jswrap_nrf_bluetooth_updateServices(JsVar *data) { + uint32_t err_code; + + if (jsvIsObject(data)) { + JsvObjectIterator it; + jsvObjectIteratorNew(&it, data); + while (jsvObjectIteratorHasValue(&it)) { + ble_uuid_t ble_uuid; + memset(&ble_uuid, 0, sizeof(ble_uuid)); + + const char *errorStr; + if ((errorStr = bleVarToUUIDAndUnLock(&ble_uuid, + jsvObjectIteratorGetKey(&it)))) { + jsExceptionHere(JSET_ERROR, "Invalid Service UUID: %s", errorStr); + break; + } + + JsVar *serviceVar = jsvObjectIteratorGetValue(&it); + JsvObjectIterator serviceit; + jsvObjectIteratorNew(&serviceit, serviceVar); + + while (jsvObjectIteratorHasValue(&serviceit)) { + ble_uuid_t char_uuid; + memset(&char_uuid, 0, sizeof(char_uuid)); + + if ((errorStr = bleVarToUUIDAndUnLock(&char_uuid, + jsvObjectIteratorGetKey(&serviceit)))) { + jsExceptionHere(JSET_ERROR, "Invalid Characteristic UUID: %s", + errorStr); + break; + } + + JsVar *charVar = jsvObjectIteratorGetValue(&serviceit); + JsVar *charValue = jsvObjectGetChild(charVar, "value", 0); + + bool notification_requested = jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "notify", 0)); + bool indication_requested = jsvGetBoolAndUnLock(jsvObjectGetChild(charVar, "indicate", 0)); + + if (charValue) { + JSV_GET_AS_CHAR_ARRAY(vPtr, vLen, charValue); + if (vPtr && vLen) { + uint8_t* p_value = (uint8_t*) vPtr; + uint16_t len = MIN(vLen, APP_CFG_CHAR_MAX_LEN); + + // Update value and notify/indicate if appropriate + uint16_t char_handle; + ble_uuid_t uuid_it; + ble_gatts_hvx_params_t hvx_params; + ble_gatts_value_t gatts_value; + + // Find the first user characteristic handle + err_code = sd_ble_gatts_initial_user_handle_get(&char_handle); + if (err_code != NRF_SUCCESS) { + APP_ERROR_CHECK(err_code); + } + + // Iterate over all handles until the correct UUID or no match is found + // We assume that handles are sequential + while (true) { + memset(&uuid_it, 0, sizeof(uuid_it)); + err_code = sd_ble_gatts_attr_get(char_handle, &uuid_it, NULL); + if (err_code == NRF_ERROR_NOT_FOUND) { + // "Out of bounds" => we went over the last known characteristic + break; + } else if (err_code == NRF_SUCCESS) { + // Valid handle => check if UUID matches + if (uuid_it.uuid == char_uuid.uuid) { + // Update the value for subsequent reads even if no client is currently connected + memset(&gatts_value, 0, sizeof(gatts_value)); + gatts_value.len = len; + gatts_value.offset = 0; + gatts_value.p_value = p_value; + err_code = sd_ble_gatts_value_set(m_conn_handle, char_handle, &gatts_value); + if (err_code != NRF_SUCCESS) { + APP_ERROR_CHECK(err_code); + } + + // Notify/indicate connected clients if necessary + if ((notification_requested || indication_requested) && (m_conn_handle != BLE_CONN_HANDLE_INVALID)) { + memset(&hvx_params, 0, sizeof(hvx_params)); + hvx_params.handle = char_handle; + hvx_params.type = indication_requested ? BLE_GATT_HVX_INDICATION : BLE_GATT_HVX_NOTIFICATION; + hvx_params.offset = 0; + hvx_params.p_len = &len; + hvx_params.p_data = p_value; + + err_code = sd_ble_gatts_hvx(m_conn_handle, &hvx_params); + if ((err_code != NRF_SUCCESS) + && (err_code != NRF_ERROR_INVALID_STATE) + && (err_code != BLE_ERROR_NO_TX_PACKETS) + && (err_code != BLE_ERROR_GATTS_SYS_ATTR_MISSING)) { + APP_ERROR_CHECK(err_code); + } + } + break; + } + } else { + APP_ERROR_CHECK(err_code); + } + char_handle++; + } + } + } + + jsvUnLock(charValue); + jsvUnLock(charVar); + + jsvObjectIteratorNext(&serviceit); + } + jsvObjectIteratorFree(&serviceit); + jsvUnLock(serviceVar); + + jsvObjectIteratorNext(&it); + } + jsvObjectIteratorFree(&it); + + } else if (!jsvIsUndefined(data)) { + jsExceptionHere(JSET_TYPEERROR, "Expecting object or undefined, got %t", + data); + } +} /*JSON{ "type" : "staticmethod", diff --git a/libs/bluetooth/jswrap_bluetooth.h b/libs/bluetooth/jswrap_bluetooth.h index 0c6cd7137..6d81d1237 100644 --- a/libs/bluetooth/jswrap_bluetooth.h +++ b/libs/bluetooth/jswrap_bluetooth.h @@ -26,6 +26,7 @@ void jswrap_nrf_bluetooth_wake(void); JsVarFloat jswrap_nrf_bluetooth_getBattery(void); void jswrap_nrf_bluetooth_setAdvertising(JsVar *data, JsVar *options); void jswrap_nrf_bluetooth_setServices(JsVar *data); +void jswrap_nrf_bluetooth_updateServices(JsVar *data); void jswrap_nrf_bluetooth_setScan(JsVar *callback); void jswrap_nrf_bluetooth_setTxPower(JsVarInt pwr); diff --git a/libs/crypto/jswrap_crypto.c b/libs/crypto/jswrap_crypto.c index 844bb6fb9..9dc352275 100644 --- a/libs/crypto/jswrap_crypto.c +++ b/libs/crypto/jswrap_crypto.c @@ -38,7 +38,7 @@ } Cryptographic functions -**Note:** This library is currently only included in builds for the Espruino Pico. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room. +**Note:** This library is currently only included in builds for the Espruino Pico and Espruino WiFi. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room. */ @@ -50,7 +50,7 @@ Cryptographic functions } Class containing AES encryption/decryption -**Note:** This library is currently only included in builds for the Espruino Pico. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room. +**Note:** This library is currently only included in builds for the Espruino Pico and Espruino WiFi. For other boards you will have to make build your own firmware, and you may need to remove other features in order to make room. */ /*JSON{ "type" : "staticproperty", @@ -449,4 +449,4 @@ JsVar *jswrap_crypto_AES_encrypt(JsVar *message, JsVar *key, JsVar *options) { JsVar *jswrap_crypto_AES_decrypt(JsVar *message, JsVar *key, JsVar *options) { return jswrap_crypto_AEScrypt(message, key, options, false); } -#endif \ No newline at end of file +#endif diff --git a/libs/network/esp8266/jswrap_esp8266_network.c b/libs/network/esp8266/jswrap_esp8266_network.c index 6d46a681e..6ede0a7bd 100644 --- a/libs/network/esp8266/jswrap_esp8266_network.c +++ b/libs/network/esp8266/jswrap_esp8266_network.c @@ -1657,7 +1657,7 @@ Perform a network ping request. The parameter can be either a String or a numeri void jswrap_ESP8266_ping( JsVar *ipAddr, //!< A string or integer representation of an IP address. JsVar *pingCallback //!< Optional callback function. - ) { +) { memset(&pingOpt, 0, sizeof(pingOpt)); // If the parameter is a string, get the IP address from the string // representation. @@ -2001,7 +2001,7 @@ static void wifiEventHandler(System_Event_t *evt) { int rssi = evt->event_info.ap_probereqrecved.rssi; if (rssi > 0) rssi = 0; jsvObjectSetChildAndUnLock(jsDetails, "rssi", jsvNewFromInteger(rssi)); - mac = evt->event_info.sta_connected.mac; + mac = evt->event_info.ap_probereqrecved.mac; os_sprintf(macAddrString, macFmt, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); jsvObjectSetChildAndUnLock(jsDetails, "mac", jsvNewFromString(macAddrString)); sendWifiEvent(evt->event, jsDetails); diff --git a/libs/network/esp8266/ota.c b/libs/network/esp8266/ota.c index 5ec8a48c9..cc46c4787 100644 --- a/libs/network/esp8266/ota.c +++ b/libs/network/esp8266/ota.c @@ -87,12 +87,13 @@ static void sendResponse(OtaConn *oc, uint16_t code, char *text) { * * It returns an error string if something is amiss */ -static char* check_header(void *buf) { +static char* check_header(void *buf, int which) { uint8_t *cd = (uint8_t *)buf; uint32_t *buf32 = buf; os_printf("OTA hdr %p: %08lX %08lX %08lX %08lX\n", buf, buf32[0], buf32[1], buf32[2], buf32[3]); if (cd[0] != 0xEA) return "IROM magic missing"; if (cd[1] != 4 || cd[2] > 3 || (cd[3]>>4) > 6) return "bad flash header"; + if (cd[3] < 3 && cd[3] != which) return "Wrong partition binary"; if (((uint16_t *)buf)[3] != 0x4010) return "Invalid entry addr"; if (((uint32_t *)buf)[2] != 0) return "Invalid start offset"; return NULL; @@ -153,8 +154,11 @@ static int16_t otaHandleUpload(OtaConn *oc) { uint16_t toFlash = OTA_CHUNK_SZ; if (oc->rxBufFill < toFlash) toFlash = oc->rxBufFill; + // let's see which partition we need to flash + uint8 id = system_upgrade_userbin_check(); + // check that data starts with an appropriate header - if (err == NULL && offset == 0) err = check_header(oc->rxBuffer+oc->rxBufOff); + if (err == NULL && offset == 0) err = check_header(oc->rxBuffer+oc->rxBufOff, 1-id); // return an error if there is one if (err != NULL) { @@ -163,8 +167,7 @@ static int16_t otaHandleUpload(OtaConn *oc) { return -1; } - // let's see which partition we need to flash and what flash address that puts us at - uint8 id = system_upgrade_userbin_check(); + // let's see which what flash address we're uploading to uint32_t address = id ? 0x1000 : flashUser2Addr[flashSizeMap]; address += offset; @@ -200,7 +203,7 @@ static int16_t otaHandleReboot(OtaConn *oc) { uint32 buf[8]; spi_flash_read(address, buf, sizeof(buf)); - char *err = check_header(buf); + char *err = check_header(buf, 1-id); if (err != NULL) { os_printf("OTA Error %d: %s\n", 400, err); sendResponse(oc, 400, err); diff --git a/libs/network/jswrap_net.c b/libs/network/jswrap_net.c index 1717b6298..c085bd674 100644 --- a/libs/network/jswrap_net.c +++ b/libs/network/jswrap_net.c @@ -468,6 +468,8 @@ You can also: For more information about generating and using certificates, see: https://engineering.circle.com/https-authorized-certs-with-node-js/ + +(You'll need to use 2048 bit certificates as opposed to 4096 bit shown above) */ // --------------------------------------------------------------------------------- diff --git a/libs/network/telnet/jswrap_telnet.c b/libs/network/telnet/jswrap_telnet.c index e59dccd60..bcadf67ff 100644 --- a/libs/network/telnet/jswrap_telnet.c +++ b/libs/network/telnet/jswrap_telnet.c @@ -66,7 +66,7 @@ static uint8_t tnSrvMode; // current mode for the telnet server /*JSON{ "type" : "library", - "class" : "Telnet" + "class" : "TelnetServer" } This library implements a telnet console for the Espruino interpreter. It requires a network connection, e.g. Wifi, and **currently only functions on the ESP8266 and on Linux **. It uses @@ -77,7 +77,7 @@ port 23 on the ESP8266 and port 2323 on Linux. /*JSON{ "type" : "staticmethod", - "class" : "Telnet", + "class" : "TelnetServer", "name" : "setOptions", "generate" : "jswrap_telnet_setOptions", "params": [ @@ -110,7 +110,7 @@ void jswrap_telnet_setOptions(JsVar *jsOptions) { /*JSON{ "type" : "init", - "class" : "Telnet", + "class" : "TelnetServer", "generate" : "jswrap_telnet_init" } */ @@ -124,7 +124,7 @@ void jswrap_telnet_init(void) { /*JSON{ "type" : "kill", - "class" : "Telnet", + "class" : "TelnetServer", "generate" : "jswrap_telnet_kill" } */ @@ -134,7 +134,7 @@ void jswrap_telnet_kill(void) { /*JSON{ "type" : "idle", - "class" : "Telnet", + "class" : "TelnetServer", "generate" : "jswrap_telnet_idle" } */ @@ -226,7 +226,12 @@ void telnetRelease(JsNetwork *net) { printf("tnSrv: released console from sock %d\n", tnSrv.cliSock); netCloseSocket(net, tnSrv.cliSock); tnSrv.cliSock = 0; - if (!jsiIsConsoleDeviceForced()) jsiSetConsoleDevice(tnSrv.oldConsole, false); + IOEventFlags console = jsiGetConsoleDevice(); + // only switch away from telnet if the current console is TELNET, this allows the current + // console to be set to something else while connected via telnet and then not have it + // switched again when disconnecting from telnet + if (console == EV_TELNET && !jsiIsConsoleDeviceForced()) + jsiSetConsoleDevice(tnSrv.oldConsole, false); } // Attempt to send buffer on an established client connection, returns true if it sent something diff --git a/libs/puckjs/jswrap_puck.c b/libs/puckjs/jswrap_puck.c index 96b6672ef..8a9f8fbd3 100644 --- a/libs/puckjs/jswrap_puck.c +++ b/libs/puckjs/jswrap_puck.c @@ -35,6 +35,10 @@ // Has the magnetometer been turned on? bool mag_enabled = false; +/* TODO: Use software I2C for this instead. Since we're relying + * on the internal pullup resistors there might be some gotchas + * since we force high here for 0.1uS here before going open circuit. */ + void wr(int pin, bool state) { if (state) { nrf_gpio_pin_set(pin); nrf_gpio_cfg_output(pin); @@ -138,7 +142,6 @@ uint8_t i2c_rd(bool nack) { return data; } - // Turn magnetometer on and configure bool mag_on(int milliHz) { int reg1 = 0; @@ -172,14 +175,14 @@ bool mag_on(int milliHz) { reg1 |= 1; // Active bit i2c_wr(reg1); i2c_stop(); -return true; + return true; } // Wait for magnetometer IRQ line to be set void mag_wait() { int timeout = I2C_TIMEOUT*2; while (!nrf_gpio_pin_read(MAG_INT) && --timeout); - if (!timeout) err("Timeout (wait reading)"); + if (!timeout) jsExceptionHere(JSET_INTERNALERROR, "Timeout (Magnetometer)"); } // Read a value @@ -229,6 +232,22 @@ Class containing [Puck.js's](http://www.puck-js.com) utility functions. "return" : ["JsVar", "An Object `{x,y,z}` of magnetometer readings as integers" ] } Turn on the magnetometer, take a single reading, and then turn it off again. + +An object of the form `{x,y,z}' is returned containing magnetometer readings. +Due to residual magnetism in the Puck and magnetometer itself, with +no magnetic field the Puck will not return `{x:0,y:0,z:0}`. + +Instead, it's up to you to figure out what the 'zero value' is for your +Puck in your location and to then subtract that from the value returned. If +you're not trying to measure the Earth's magnetic field then it's a good idea +to just take a reading at startup and use that. + +With the aerial at the top of the board, the `y` reading is vertical, `x` is +horizontal, and `z` is through the board. + +Readings are in increments of 0.1 micro Tesla (uT). The Earth's magnetic field +varies from around 25-60 uT, so the reading will vary by 250 to 600 depending +on location. */ JsVar *jswrap_puck_mag() { if (!mag_enabled) mag_on(80000); @@ -247,12 +266,9 @@ JsVar *jswrap_puck_mag() { Called after `Puck.magOn()` every time magnetometer data is discovered. There is one argument which is an object of the form `{x,y,z}' containing magnetometer readings -as integers. +as integers (for more information see `Puck.mag()`. */ -void _jswrap_mag_irq() { -} - /*JSON{ "type" : "staticmethod", "class" : "Puck", @@ -396,6 +412,35 @@ int jswrap_puck_capSense(Pin tx, Pin rx) { return (int)nrf_utils_cap_sense(CAPSENSE_TX_PIN, CAPSENSE_RX_PIN); } +/*JSON{ + "type" : "staticmethod", + "class" : "Puck", + "name" : "light", + "#ifdef" : "NRF52", + "generate" : "jswrap_puck_light", + "return" : ["float", "A light value from 0 to 1" ] +} +Read a light value based on the light the red LED is seeing +*/ +JsVarFloat jswrap_puck_light() { + // If pin state wasn't an analog input before, make it one now, + // read, and delay, just to make sure everything has time to settle + // before the 'real' reading + JshPinState s = jshPinGetState(LED1_PININDEX); + if (s != JSHPINSTATE_GPIO_IN) { + jshPinOutput(LED1_PININDEX,0);// discharge + jshPinAnalog(LED1_PININDEX);// analog + jshDelayMicroseconds(5000); + } + JsVarFloat f = jshPinAnalog(LED1_PININDEX)/0.45; + if (f>1) f=1; + // turn the red LED back on if it was on before + if (s & JSHPINSTATE_PIN_IS_ON) + jshPinOutput(LED1_PININDEX, 1); + + return f; +} + /*JSON{ "type" : "kill", "generate" : "jswrap_puck_kill" diff --git a/libs/puckjs/jswrap_puck.h b/libs/puckjs/jswrap_puck.h index ca8a3a3db..bb7eb4ddc 100644 --- a/libs/puckjs/jswrap_puck.h +++ b/libs/puckjs/jswrap_puck.h @@ -18,6 +18,7 @@ void jswrap_puck_magOff(); JsVar *jswrap_puck_mag(); void jswrap_puck_IR(JsVar *data); int jswrap_puck_capSense(Pin tx, Pin rx); +JsVarFloat jswrap_puck_light(); void jswrap_puck_kill(); bool jswrap_puck_idle(); diff --git a/libs/tv/tv.c b/libs/tv/tv.c index 99ad6ca2f..bb5a3f1ce 100644 --- a/libs/tv/tv.c +++ b/libs/tv/tv.c @@ -271,7 +271,7 @@ void tv_vga_irq() { jshPinSetValue(tvPinSyncV, tvCurrentLine>=2); // 2 lines of sync jshDelayMicroseconds(1); jshPinSetValue(tvPinSync, 1); - jshDelayMicroseconds(1); + jshDelayMicroseconds(2); uint32_t lineIdx = ((uint32_t)tvCurrentLine - 20) / tvLineRepeat; // 20px = front porch if (lineIdx < tvHeight) { diff --git a/scripts/common.py b/scripts/common.py index a126bc2f3..b75d401df 100644 --- a/scripts/common.py +++ b/scripts/common.py @@ -313,14 +313,14 @@ def get_prefix_name(jsondata): def get_ifdef_description(d): if d=="SAVE_ON_FLASH": return "devices with low flash memory" - if d=="STM32F1": return "STM32F1 devices (including Espruino Board)" + if d=="STM32F1": return "STM32F1 devices (including Original Espruino Board)" if d=="USE_LCD_SDL": return "Linux with SDL support compiled in" - if d=="USE_TLS": return "devices with TLS and SSL support (Espruino Pico only)" + if d=="USE_TLS": return "devices with TLS and SSL support (Espruino Pico and Espruino WiFi only)" if d=="RELEASE": return "release builds" if d=="LINUX": return "Linux-based builds" - if d=="USE_USB_HID": return "devices that support USB HID (Espruino Pico)" - if d=="USE_AES": return "devices that support AES (Espruino Pico, Espruino Wifi or Linux)" - if d=="USE_CRYPTO": return "devices that support Crypto Functionality (Espruino Pico, Espruino Wifi, Linux or ESP8266)" + if d=="USE_USB_HID": return "devices that support USB HID (Espruino Pico and Espruino WiFi)" + if d=="USE_AES": return "devices that support AES (Espruino Pico, Espruino WiFi or Linux)" + if d=="USE_CRYPTO": return "devices that support Crypto Functionality (Espruino Pico, Espruino WiFi, Linux or ESP8266)" print("WARNING: Unknown ifdef '"+d+"' in common.get_ifdef_description") return d diff --git a/src/jsdevices.c b/src/jsdevices.c index ffdfa5be5..d51a01518 100644 --- a/src/jsdevices.c +++ b/src/jsdevices.c @@ -319,7 +319,7 @@ void CALLED_FROM_INTERRUPT jshPushIOWatchEvent( // If there is a callback associated with this GPIO event then invoke // it and we are done. if (jshEventCallbacks[channel-EV_EXTI0]) { - jshEventCallbacks[channel-EV_EXTI0](state); + jshEventCallbacks[channel-EV_EXTI0](state, channel); return; } diff --git a/src/jsdevices.h b/src/jsdevices.h index fcc8f562f..071a8c478 100644 --- a/src/jsdevices.h +++ b/src/jsdevices.h @@ -185,7 +185,7 @@ void jshSetFlowControlXON(IOEventFlags device, bool hostShouldTransmit); void jshSetFlowControlEnabled(IOEventFlags device, bool xOnXOff); // Functions that can be called in an IRQ when a pin changes state -typedef void(*JshEventCallbackCallback)(bool state); +typedef void(*JshEventCallbackCallback)(bool state, IOEventFlags flags); /// Set a callback function to be called when an event occurs void jshSetEventCallback(IOEventFlags channel, JshEventCallbackCallback callback); diff --git a/src/jshardware.h b/src/jshardware.h index f5d879823..89ff52f07 100644 --- a/src/jshardware.h +++ b/src/jshardware.h @@ -101,7 +101,8 @@ bool jshPinGetValue(Pin pin); ///< Get the value of a digital input. DOES NOT ch typedef enum { JSHPINSTATE_UNDEFINED, ///< Used when getting the pin state, if we have no idea what it is. JSHPINSTATE_GPIO_OUT, ///< GPIO pin as totem pole output - JSHPINSTATE_GPIO_OUT_OPENDRAIN, ///< GPIO pin as open-collector/open-drain output WITH PULLUP + JSHPINSTATE_GPIO_OUT_OPENDRAIN, ///< GPIO pin as open-collector/open-drain output WITHOUT PULLUP + JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP, ///< GPIO pin as open-collector/open-drain output WITH PULLUP JSHPINSTATE_GPIO_IN, ///< GPIO pin as input (also tri-stated output) JSHPINSTATE_GPIO_IN_PULLUP, ///< GPIO pin input with internal pull-up JSHPINSTATE_GPIO_IN_PULLDOWN, ///< GPIO pin input with internal pull-down @@ -123,6 +124,7 @@ typedef enum { #define JSHPINSTATE_IS_OUTPUT(state) ( \ (state)==JSHPINSTATE_GPIO_OUT || \ (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \ + (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \ (state)==JSHPINSTATE_AF_OUT || \ (state)==JSHPINSTATE_AF_OUT_OPENDRAIN || \ (state)==JSHPINSTATE_USART_OUT || \ @@ -132,6 +134,7 @@ typedef enum { /// Should a pin of this state be Open Drain? #define JSHPINSTATE_IS_OPENDRAIN(state) ( \ (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \ + (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \ (state)==JSHPINSTATE_AF_OUT_OPENDRAIN || \ (state)==JSHPINSTATE_I2C || \ 0) @@ -146,6 +149,7 @@ typedef enum { /// Should a pin of this state have an internal pullup? #define JSHPINSTATE_IS_PULLUP(state) ( \ (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN || \ + (state)==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP || \ (state)==JSHPINSTATE_GPIO_IN_PULLUP || \ (state)==JSHPINSTATE_USART_IN || \ 0) @@ -303,8 +307,8 @@ void jshSPIWait(IOEventFlags device); typedef struct { Pin pinSCL; Pin pinSDA; - int bitrate; - // timeout? + int bitrate; ///< bits per second + bool started; ///< Has I2C 'start' condition been sent so far? } PACKED_FLAGS JshI2CInfo; /// Initialise a JshI2CInfo struct to default settings diff --git a/src/jshardware_common.c b/src/jshardware_common.c index a0084437c..3aa716a0f 100644 --- a/src/jshardware_common.c +++ b/src/jshardware_common.c @@ -38,4 +38,5 @@ void jshI2CInitInfo(JshI2CInfo *inf) { inf->pinSCL = PIN_UNDEFINED; inf->pinSDA = PIN_UNDEFINED; inf->bitrate = 50000; // Is what we used - shouldn't it be 100k? + inf->started = false; } diff --git a/src/jsi2c.c b/src/jsi2c.c new file mode 100644 index 000000000..ba2a46505 --- /dev/null +++ b/src/jsi2c.c @@ -0,0 +1,168 @@ +/* + * This file is part of Espruino, a JavaScript interpreter for Microcontrollers + * + * Copyright (C) 2013 Gordon Williams + * + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. + * + * ---------------------------------------------------------------------------- + * I2C Utility functions, and software I2C + * ---------------------------------------------------------------------------- + */ +#include "jsi2c.h" +#include "jsinteractive.h" + +typedef struct { + Pin pinSCL; + Pin pinSDA; + bool started; + int delay; +} i2cInfo; + +bool jsi2cPopulateI2CInfo( + JshI2CInfo *inf, + JsVar *options + ) { + jshI2CInitInfo(inf); + + jsvConfigObject configs[] = { + {"scl", JSV_PIN, &inf->pinSCL}, + {"sda", JSV_PIN, &inf->pinSDA}, + {"bitrate", JSV_INTEGER, &inf->bitrate} + }; + if (jsvReadConfigObject(options, configs, sizeof(configs) / sizeof(jsvConfigObject))) { + return true; + } else + return false; +} + +// -------------------------------------------------------- I2C Implementation + +const int I2C_TIMEOUT = 100000; + +static void dly(i2cInfo *inf) { + volatile int i; + for (i=inf->delay;i>0;i--); +} + +static void err(const char *s) { + jsExceptionHere(JSET_ERROR, "I2C Error: %s", s); +} + +static void i2c_start(i2cInfo *inf) { + if (inf->started) { + // reset + jshPinSetValue(inf->pinSDA, 1); + dly(inf); + jshPinSetValue(inf->pinSCL, 1); + int timeout = I2C_TIMEOUT; + while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch + if (!timeout) err("Timeout (start)"); + dly(inf); + } + if (!jshPinGetValue(inf->pinSDA)) err("Arbitration (start)"); + jshPinSetValue(inf->pinSDA, 0); + dly(inf); + jshPinSetValue(inf->pinSCL, 0); + dly(inf); + inf->started = true; +} + +static void i2c_stop(i2cInfo *inf) { + jshPinSetValue(inf->pinSDA, 0); + dly(inf); + jshPinSetValue(inf->pinSCL, 1); + int timeout = I2C_TIMEOUT; + while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch + if (!timeout) err("Timeout (stop)"); + dly(inf); + jshPinSetValue(inf->pinSDA, 1); + dly(inf); + if (!jshPinGetValue(inf->pinSDA)) err("Arbitration (stop)"); + dly(inf); + inf->started = false; +} + +static void i2c_wr_bit(i2cInfo *inf, bool b) { + jshPinSetValue(inf->pinSDA, b); + dly(inf); + jshPinSetValue(inf->pinSCL, 1); + dly(inf); + int timeout = I2C_TIMEOUT; + while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch + if (!timeout) err("Timeout (wr)"); + jshPinSetValue(inf->pinSCL, 0); + jshPinSetValue(inf->pinSDA, 1); // stop forcing SDA (needed?) +} + +static bool i2c_rd_bit(i2cInfo *inf) { + jshPinSetValue(inf->pinSDA, 1); // stop forcing SDA + dly(inf); + jshPinSetValue(inf->pinSCL, 1); // stop forcing SDA + int timeout = I2C_TIMEOUT; + while (!jshPinGetValue(inf->pinSCL) && --timeout); // clock stretch + if (!timeout) err("Timeout (rd)"); + dly(inf); + bool b = jshPinGetValue(inf->pinSDA); + jshPinSetValue(inf->pinSCL, 0); + return b; +} + +// true on ack, false on nack +static bool i2c_wr(i2cInfo *inf, uint8_t data) { + int i; + for (i=0;i<8;i++) { + i2c_wr_bit(inf, data&128); + data <<= 1; + } + return !i2c_rd_bit(inf); +} + +static uint8_t i2c_rd(i2cInfo *inf, bool nack) { + int i; + int data = 0; + for (i=0;i<8;i++) + data = (data<<1) | (i2c_rd_bit(inf)?1:0); + i2c_wr_bit(inf, nack); + return data; +} + + +static void i2c_initstruct(i2cInfo *inf, JshI2CInfo *i) { + inf->pinSDA = i->pinSDA; + inf->pinSCL = i->pinSCL; + inf->started = i->started; + inf->delay = 4000000/i->bitrate; +} + +// ---------------------------------------------------------------------------- + +void jsi2cWrite(JshI2CInfo *inf, unsigned char address, int nBytes, const unsigned char *data, bool sendStop) { + if (inf->pinSCL==PIN_UNDEFINED || inf->pinSDA==PIN_UNDEFINED) + return; + i2cInfo d; + i2c_initstruct(&d, inf); + i2c_start(&d); + i2c_wr(&d, address<<1); + int i; + for (i=0;istarted = d.started; +} + +void jsi2cRead(JshI2CInfo *inf, unsigned char address, int nBytes, unsigned char *data, bool sendStop) { + if (inf->pinSCL==PIN_UNDEFINED || inf->pinSDA==PIN_UNDEFINED) + return; + i2cInfo d; + i2c_initstruct(&d, inf); + i2c_start(&d); + i2c_wr(&d, 1|(address<<1)); + int i; + for (i=0;istarted = d.started; +} diff --git a/src/jsi2c.h b/src/jsi2c.h new file mode 100644 index 000000000..428290d71 --- /dev/null +++ b/src/jsi2c.h @@ -0,0 +1,23 @@ +/* + * This file is part of Espruino, a JavaScript interpreter for Microcontrollers + * + * Copyright (C) 2013 Gordon Williams + * + * This Source Code Form is subject to the terms of the Mozilla Public + * License, v. 2.0. If a copy of the MPL was not distributed with this + * file, You can obtain one at http://mozilla.org/MPL/2.0/. + * + * ---------------------------------------------------------------------------- + * I2C Utility functions, and software I2C + * ---------------------------------------------------------------------------- + */ +#include "jsvar.h" +#include "jshardware.h" + +bool jsi2cPopulateI2CInfo( + JshI2CInfo *inf, + JsVar *options + ); + +void jsi2cWrite(JshI2CInfo *inf, unsigned char address, int nBytes, const unsigned char *data, bool sendStop); +void jsi2cRead(JshI2CInfo *inf, unsigned char address, int nBytes, unsigned char *data, bool sendStop); diff --git a/src/jsinteractive.c b/src/jsinteractive.c index 43954ce41..6adff3177 100644 --- a/src/jsinteractive.c +++ b/src/jsinteractive.c @@ -665,13 +665,12 @@ void jsiDumpHardwareInitialisation(vcbprintf_callback user_callback, void *user_ statem == BTN1_PINSTATE) continue; #endif // don't bother with normal inputs, as they come up in this state (ish) anyway - const char *s = 0; - // JSHPINSTATE_GPIO_IN is the default - don't do anything for it - if (statem == JSHPINSTATE_GPIO_IN_PULLUP) s="input_pullup"; - else if (statem == JSHPINSTATE_GPIO_IN_PULLDOWN) s="input_pulldown"; - else if (statem == JSHPINSTATE_GPIO_OUT) s="output"; - else if (statem == JSHPINSTATE_GPIO_OUT_OPENDRAIN) s="opendrain"; - if (s) cbprintf(user_callback, user_data, "pinMode(%p, \"%s\");\n",pin,s); + if (statem != JSHPINSTATE_GPIO_IN) { + // use getPinMode to get the correct string (remove some duplication) + JsVar *s = jswrap_io_getPinMode(pin); + if (s) cbprintf(user_callback, user_data, "pinMode(%p, %q);\n",pin,s); + jsvUnLock(s); + } } } @@ -1345,7 +1344,7 @@ void jsiHandleNewLine(bool execute) { void jsiHandleChar(char ch) { - // jsiConsolePrintf("[%d:%d]\n", inputState, ch); + //jsiConsolePrintf("[%d:%d]\n", inputState, ch); // // special stuff // 1 - Ctrl-a - beginning of line @@ -1358,6 +1357,8 @@ void jsiHandleChar(char ch) { // 27 then 91 then 67 ('C') - right // 27 then 91 then 65 ('A') - up // 27 then 91 then 66 ('B') - down + // 27 then 91 then 70 - home + // 27 then 91 then 72 - end // // 27 then 91 then 48-57 (numeric digits) then 'd' - set line number, used for that // inputLine and put into any declared functions @@ -1457,7 +1458,9 @@ void jsiHandleChar(char ch) { jsiChangeToHistory(false); // if at end of line else jsiHandleMoveUpDown(1); - } + } else if (ch == 70) jsiHandleEnd(); + else if (ch == 72) jsiHandleHome(); + else jsiConsolePrintf("[%d:%d]\n", inputState, ch); } else if (inputState==IS_HAD_27_91_NUMBER) { if (ch>='0' && ch<='9') { inputStateNumber = (uint16_t)(10*inputStateNumber + ch - '0'); diff --git a/src/jslex.c b/src/jslex.c index fe59dd71d..394f05c0d 100644 --- a/src/jslex.c +++ b/src/jslex.c @@ -170,7 +170,7 @@ const jslJumpTableEnum jslJumpTable[jslJumpTableEnd+1-jslJumpTableStart] = { JSLJT_TOPHAT, // ^ JSLJT_ID, // _ // 96 - JSLJT_SINGLECHAR, // ` + JSLJT_STRING, // ` JSLJT_ID, // A lowercase JSLJT_ID, // B lowercase JSLJT_ID, // C lowercase @@ -428,7 +428,10 @@ void jslGetNextToken() { } } jsvStringIteratorFree(&it); - lex->tk = lex->currCh==delim ? LEX_STR : LEX_UNFINISHED_STR; + if (lex->currCh==delim) { + lex->tk = delim=='`' ? LEX_TEMPLATE_LITERAL : LEX_STR; + } else + lex->tk = LEX_UNFINISHED_STR; jslGetNextCh(); } break; case JSLJT_EXCLAMATION: jslSingleChar(); @@ -500,6 +503,9 @@ void jslGetNextToken() { lex->tk = LEX_TYPEEQUAL; jslGetNextCh(); } + } else if (lex->currCh=='>') { // => + lex->tk = LEX_ARROW_FUNCTION; + jslGetNextCh(); } break; case JSLJT_LESSTHAN: jslSingleChar(); if (lex->currCh=='=') { // <= @@ -618,6 +624,7 @@ void jslTokenAsString(int token, char *str, size_t len) { case LEX_INT : strncpy(str, "INT", len); return; case LEX_FLOAT : strncpy(str, "FLOAT", len); return; case LEX_STR : strncpy(str, "STRING", len); return; + case LEX_TEMPLATE_LITERAL : strncpy(str, "TEMPLATE LITERAL", len); return; case LEX_UNFINISHED_STR : strncpy(str, "UNFINISHED STRING", len); return; } if (token>=LEX_EQUAL && token\0" // reserved words /*LEX_R_IF : */ "if\0" diff --git a/src/jslex.h b/src/jslex.h index 979ba315e..56f83a028 100644 --- a/src/jslex.h +++ b/src/jslex.h @@ -24,6 +24,7 @@ typedef enum LEX_TYPES { LEX_INT, LEX_FLOAT, LEX_STR, + LEX_TEMPLATE_LITERAL, LEX_UNFINISHED_STR, LEX_UNFINISHED_COMMENT, @@ -51,6 +52,7 @@ typedef enum LEX_TYPES { LEX_OREQUAL, LEX_OROR, LEX_XOREQUAL, + LEX_ARROW_FUNCTION, // reserved words #define LEX_R_LIST_START LEX_R_IF LEX_R_IF, diff --git a/src/jsparse.c b/src/jsparse.c index 81996173b..9edb7cbaf 100644 --- a/src/jsparse.c +++ b/src/jsparse.c @@ -343,62 +343,53 @@ NO_INLINE bool jspeFunctionArguments(JsVar *funcVar) { return true; } -NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) { - // actually parse a function... We assume that the LEX_FUNCTION and name - // have already been parsed - JsVar *funcVar = 0; - - bool actuallyCreateFunction = JSP_SHOULD_EXECUTE; - if (actuallyCreateFunction) - funcVar = jsvNewWithFlags(JSV_FUNCTION); - - JsVar *functionInternalName = 0; - if (parseNamedFunction && lex->tk==LEX_ID) { - // you can do `var a = function foo() { foo(); };` - so cope with this - if (funcVar) functionInternalName = jslGetTokenValueAsVar(lex); - // note that we don't add it to the beginning, because it would mess up our function call code - JSP_ASSERT_MATCH(LEX_ID); - } - - // Get arguments save them to the structure - if (!jspeFunctionArguments(funcVar)) { - jsvUnLock2(functionInternalName, funcVar); - // parse failed - return 0; - } - JSP_MATCH_WITH_CLEANUP_AND_RETURN('{',jsvUnLock(funcVar),0); - -#ifndef SAVE_ON_FLASH - if (lex->tk==LEX_STR && !strcmp(jslGetTokenValueAsString(lex), "compiled")) { - jsWarn("Function marked with \"compiled\" uploaded in source form"); - } -#endif - - /* If the function starts with return, treat it specially - - * we don't want to store the 'return' part of it - */ - if (funcVar && lex->tk==LEX_R_RETURN) { +// Parse function, assuming we're on '{' +NO_INLINE bool jspeFunctionDefinitionInternal(JsVar *funcVar, bool expressionOnly) { + if (expressionOnly) { funcVar->flags = (funcVar->flags & ~JSV_VARTYPEMASK) | JSV_FUNCTION_RETURN; - JSP_ASSERT_MATCH(LEX_R_RETURN); + } else { + JSP_MATCH('{'); + + #ifndef SAVE_ON_FLASH + if (lex->tk==LEX_STR && !strcmp(jslGetTokenValueAsString(lex), "compiled")) { + jsWarn("Function marked with \"compiled\" uploaded in source form"); + } + #endif + + /* If the function starts with return, treat it specially - + * we don't want to store the 'return' part of it + */ + if (funcVar && lex->tk==LEX_R_RETURN) { + funcVar->flags = (funcVar->flags & ~JSV_VARTYPEMASK) | JSV_FUNCTION_RETURN; + JSP_ASSERT_MATCH(LEX_R_RETURN); + } } // Get the line number (if needed) JsVarInt lineNumber = 0; - if (actuallyCreateFunction && lex->lineNumberOffset) { + if (funcVar && lex->lineNumberOffset) { // jslGetLineNumber is slow, so we only do it if we have debug info lineNumber = (JsVarInt)jslGetLineNumber(lex) + (JsVarInt)lex->lineNumberOffset - 1; } // Get the code - parse it and figure out where it stops JslCharPos funcBegin = jslCharPosClone(&lex->tokenStart); - int brackets = 0; int lastTokenEnd = -1; - while (lex->tk && (brackets || lex->tk != '}')) { - if (lex->tk == '{') brackets++; - if (lex->tk == '}') brackets--; - lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->it)-1; - JSP_ASSERT_MATCH(lex->tk); + if (!expressionOnly) { + int brackets = 0; + while (lex->tk && (brackets || lex->tk != '}')) { + if (lex->tk == '{') brackets++; + if (lex->tk == '}') brackets--; + lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->it)-1; + JSP_ASSERT_MATCH(lex->tk); + } + } else { + JsExecFlags oldExec = execInfo.execute; + execInfo.execute = EXEC_NO; + jsvUnLock(jspeAssignmentExpression()); + execInfo.execute = oldExec; + lastTokenEnd = (int)jsvStringIteratorGetIndex(&lex->tokenStart.it)-1; } // Then create var and set (if there was any code!) - if (actuallyCreateFunction && lastTokenEnd>0) { + if (funcVar && lastTokenEnd>0) { // code var JsVar *funcCodeVar; if (jsvIsNativeString(lex->sourceVar)) { @@ -426,13 +417,44 @@ NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) { jsvUnLock2(jsvAddNamedChild(funcVar, funcLineNumber, JSPARSE_FUNCTION_LINENUMBER_NAME), funcLineNumber); } } - // if we had a function name, add it to the end - if (functionInternalName) - jsvObjectSetChildAndUnLock(funcVar, JSPARSE_FUNCTION_NAME_NAME, functionInternalName); } jslCharPosFree(&funcBegin); - JSP_MATCH_WITH_CLEANUP_AND_RETURN('}',jsvUnLock(funcVar),0); + if (!expressionOnly) JSP_MATCH('}'); + return 0; +} + +// Parse function (after 'function' has occurred +NO_INLINE JsVar *jspeFunctionDefinition(bool parseNamedFunction) { + // actually parse a function... We assume that the LEX_FUNCTION and name + // have already been parsed + JsVar *funcVar = 0; + + bool actuallyCreateFunction = JSP_SHOULD_EXECUTE; + if (actuallyCreateFunction) + funcVar = jsvNewWithFlags(JSV_FUNCTION); + + JsVar *functionInternalName = 0; + if (parseNamedFunction && lex->tk==LEX_ID) { + // you can do `var a = function foo() { foo(); };` - so cope with this + if (funcVar) functionInternalName = jslGetTokenValueAsVar(lex); + // note that we don't add it to the beginning, because it would mess up our function call code + JSP_ASSERT_MATCH(LEX_ID); + } + + // Get arguments save them to the structure + if (!jspeFunctionArguments(funcVar)) { + jsvUnLock2(functionInternalName, funcVar); + // parse failed + return 0; + } + + // Parse the actual function block + jspeFunctionDefinitionInternal(funcVar, false); + + // if we had a function name, add it to the end + if (funcVar && functionInternalName) + jsvObjectSetChildAndUnLock(funcVar, JSPARSE_FUNCTION_NAME_NAME, functionInternalName); return funcVar; } @@ -1189,6 +1211,7 @@ NO_INLINE JsVar *jspeFactorObject() { jslGetNextToken(lex); // skip over current token } else if ( lex->tk==LEX_STR || + lex->tk==LEX_TEMPLATE_LITERAL || lex->tk==LEX_FLOAT || lex->tk==LEX_INT || lex->tk==LEX_R_TRUE || @@ -1318,10 +1341,127 @@ NO_INLINE JsVar *jspeFactorDelete() { return result; } +#ifndef SAVE_ON_FLASH +JsVar *jspeTemplateLiteral() { + JsVar *a = 0; + if (JSP_SHOULD_EXECUTE) { + JsVar *template = jslGetTokenValueAsVar(lex); + a = jsvNewFromEmptyString(); + if (a && template) { + JsvStringIterator it, dit; + jsvStringIteratorNew(&it, template, 0); + jsvStringIteratorNew(&dit, a, 0); + while (jsvStringIteratorHasChar(&it)) { + char ch = jsvStringIteratorGetChar(&it); + if (ch=='$') { + jsvStringIteratorNext(&it); + ch = jsvStringIteratorGetChar(&it); + if (ch=='{') { + // Now parse out the expression + jsvStringIteratorNext(&it); + int brackets = 1; + JsVar *expr = jsvNewFromEmptyString(); + if (!expr) break; + JsvStringIterator eit; + jsvStringIteratorNew(&eit, expr, 0); + while (jsvStringIteratorHasChar(&it)) { + ch = jsvStringIteratorGetChar(&it); + jsvStringIteratorNext(&it); + if (ch=='{') brackets++; + if (ch=='}') { + brackets--; + if (!brackets) break; + } + jsvStringIteratorAppend(&eit, ch); + } + jsvStringIteratorFree(&eit); + JsVar *result = jspEvaluateExpressionVar(expr); + jsvUnLock(expr); + result = jsvAsString(result, true); + jsvStringIteratorAppendString(&dit, result); + jsvUnLock(result); + } else { + jsvStringIteratorAppend(&dit, '$'); + } + } else { + jsvStringIteratorAppend(&dit, ch); + jsvStringIteratorNext(&it); + } + } + jsvStringIteratorFree(&it); + jsvStringIteratorFree(&dit); + } + jsvUnLock(template); + } + JSP_ASSERT_MATCH(LEX_TEMPLATE_LITERAL); + return a; +} +#endif + + +NO_INLINE JsVar *jspeAddNamedFunctionParameter(JsVar *funcVar, JsVar *name) { + if (!funcVar) funcVar = jsvNewWithFlags(JSV_FUNCTION); + char buf[JSLEX_MAX_TOKEN_LENGTH+1]; + buf[0] = '\xFF'; + jsvGetString(name, &buf[1], JSLEX_MAX_TOKEN_LENGTH); + JsVar *param = jsvAddNamedChild(funcVar, 0, buf); + jsvMakeFunctionParameter(param); + jsvUnLock(param); + return funcVar; +} + +#ifndef SAVE_ON_FLASH +// parse an arrow function +NO_INLINE JsVar *jspeArrowFunction(JsVar *funcVar, JsVar *a) { + assert(!a || jsvIsName(a)); + JSP_ASSERT_MATCH(LEX_ARROW_FUNCTION); + if (!funcVar) funcVar = jsvNewWithFlags(JSV_FUNCTION); + funcVar = jspeAddNamedFunctionParameter(funcVar, a); + + bool expressionOnly = lex->tk!='{'; + jspeFunctionDefinitionInternal(funcVar, expressionOnly); + return funcVar; +} + +// parse expressions with commas, maybe followed by an arrow function (bracket already matched) +NO_INLINE JsVar *jspeExpressionOrArrowFunction() { + JsVar *a = 0; + JsVar *funcVar = 0; + bool allNames = true; + while (lex->tk!=')' && !JSP_SHOULDNT_PARSE) { + if (allNames && jsvIsName(a)) + funcVar = jspeAddNamedFunctionParameter(funcVar, a); + jsvUnLock(a); + a = jspeAssignmentExpression(); + if (!jsvIsName(a)) allNames = false; + if (lex->tk!=')') JSP_MATCH_WITH_CLEANUP_AND_RETURN(',', jsvUnLock2(a,funcVar), 0); + } + JSP_MATCH_WITH_CLEANUP_AND_RETURN(')', jsvUnLock2(a,funcVar), 0); + // if arrow is found, create a function + if (allNames && lex->tk==LEX_ARROW_FUNCTION) { + funcVar = jspeArrowFunction(funcVar, a); + jsvUnLock(a); + return funcVar; + } else { + jsvUnLock(funcVar); + return a; + } +} +#endif + NO_INLINE JsVar *jspeFactor() { if (lex->tk==LEX_ID) { JsVar *a = jspGetNamedVariable(jslGetTokenValueAsString(lex)); JSP_ASSERT_MATCH(LEX_ID); +#ifndef SAVE_ON_FLASH + if (lex->tk==LEX_TEMPLATE_LITERAL) + jsExceptionHere(JSET_SYNTAXERROR, "Tagged template literals not supported"); + else if (lex->tk==LEX_ARROW_FUNCTION && jsvIsName(a)) { + JsVar *funcVar = jspeArrowFunction(0,a); + jsvUnLock(a); + a=funcVar; + } +#endif return a; } else if (lex->tk==LEX_INT) { JsVar *v = 0; @@ -1338,12 +1478,17 @@ NO_INLINE JsVar *jspeFactor() { JSP_ASSERT_MATCH(LEX_FLOAT); return v; } else if (lex->tk=='(') { - JsVar *a = 0; JSP_ASSERT_MATCH('('); if (!jspCheckStackPosition()) return 0; - a = jspeExpression(); +#ifdef SAVE_ON_FLASH + // Just parse a normal expression (which can include commas) + JsVar *a = jspeExpression(); if (!JSP_SHOULDNT_PARSE) JSP_MATCH_WITH_RETURN(')',a); return a; +#else + return jspeExpressionOrArrowFunction(); +#endif + } else if (lex->tk==LEX_R_TRUE) { JSP_ASSERT_MATCH(LEX_R_TRUE); return JSP_SHOULD_EXECUTE ? jsvNewFromBool(true) : 0; @@ -1357,14 +1502,15 @@ NO_INLINE JsVar *jspeFactor() { JSP_ASSERT_MATCH(LEX_R_UNDEFINED); return 0; } else if (lex->tk==LEX_STR) { - if (JSP_SHOULD_EXECUTE) { - JsVar *a = jslGetTokenValueAsVar(lex); - JSP_ASSERT_MATCH(LEX_STR); - return a; - } else { - JSP_ASSERT_MATCH(LEX_STR); - return 0; - } + JsVar *a = 0; + if (JSP_SHOULD_EXECUTE) + a = jslGetTokenValueAsVar(lex); + JSP_ASSERT_MATCH(LEX_STR); + return a; +#ifndef SAVE_ON_FLASH + } else if (lex->tk==LEX_TEMPLATE_LITERAL) { + return jspeTemplateLiteral(); +#endif } else if (lex->tk=='{') { return jspeFactorObject(); } else if (lex->tk=='[') { @@ -2311,6 +2457,7 @@ NO_INLINE JsVar *jspeStatement() { lex->tk==LEX_INT || lex->tk==LEX_FLOAT || lex->tk==LEX_STR || + lex->tk==LEX_TEMPLATE_LITERAL || lex->tk==LEX_R_NEW || lex->tk==LEX_R_NULL || lex->tk==LEX_R_UNDEFINED || @@ -2466,6 +2613,22 @@ bool jspIsConstructor(JsVar *constructor, const char *constructorName) { return isConstructor; } +/** Get the constructor of the given object, or return 0 if ot found, or not a function */ +JsVar *jspGetConstructor(JsVar *object) { + if (!jsvIsObject(object)) return 0; + JsVar *proto = jsvObjectGetChild(object, JSPARSE_INHERITS_VAR, 0); + if (jsvIsObject(proto)) { + JsVar *constr = jsvObjectGetChild(proto, JSPARSE_CONSTRUCTOR_VAR, 0); + if (jsvIsFunction(constr)) { + jsvUnLock(proto); + return constr; + } + jsvUnLock(constr); + } + jsvUnLock(proto); + return 0; +} + // ----------------------------------------------------------------------------- void jspSoftInit() { @@ -2495,6 +2658,22 @@ void jspKill() { jsvUnLock(r); } +/** Evaluate the given variable as an expression (in current scope) */ +JsVar *jspEvaluateExpressionVar(JsVar *str) { + JsLex lex; + + assert(jsvIsString(str)); + JsLex *oldLex = jslSetLex(&lex); + jslInit(str); + lex.lineNumberOffset = oldLex->lineNumberOffset; + + // actually do the parsing + JsVar *v = jspeExpression(); + jslKill(); + jslSetLex(oldLex); + + return jsvSkipNameAndUnLock(v); +} /** Execute code form a variable and return the result. If lineNumberOffset * is nonzero it's added to the line numbers that get reported for errors/debug */ @@ -2506,6 +2685,7 @@ JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset) { jslInit(str); lex.lineNumberOffset = lineNumberOffset; + JsExecInfo oldExecInfo = execInfo; execInfo.execute = EXEC_YES; bool scopeAdded = false; @@ -2529,11 +2709,7 @@ JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset) { execInfo = oldExecInfo; // It may have returned a reference, but we just want the value... - if (v) { - return jsvSkipNameAndUnLock(v); - } - // nothing returned - return 0; + return jsvSkipNameAndUnLock(v); } JsVar *jspEvaluate(const char *str, bool stringIsStatic) { diff --git a/src/jsparse.h b/src/jsparse.h index aa40fdaa4..443c7d585 100644 --- a/src/jsparse.h +++ b/src/jsparse.h @@ -26,6 +26,8 @@ void jspSoftKill(); ///< used when recovering from or saving to flash /** Returns true if the constructor function given is the same as that * of the object with the given name. */ bool jspIsConstructor(JsVar *constructor, const char *constructorName); +/** Get the constructor of the given object, or return 0 if ot found, or not a function */ +JsVar *jspGetConstructor(JsVar *object); /// Create a new built-in object that jswrapper can use to check for built-in functions JsVar *jspNewBuiltin(const char *name); @@ -53,6 +55,8 @@ JsVar *jspGetException(); /** Return a stack trace string if there was one (and clear it) */ JsVar *jspGetStackTrace(); +/** Evaluate the given variable as an expression (in current scope) */ +JsVar *jspEvaluateExpressionVar(JsVar *str); /** Execute code form a variable and return the result. If lineNumberOffset * is nonzero it's added to the line numbers that get reported for errors/debug */ JsVar *jspEvaluateVar(JsVar *str, JsVar *scope, uint16_t lineNumberOffset); diff --git a/src/jstimer.c b/src/jstimer.c index 786fe5b1a..23111e548 100644 --- a/src/jstimer.c +++ b/src/jstimer.c @@ -129,7 +129,8 @@ void jstUtilTimerInterruptHandler() { // now search for other tasks writing to this pin... (polyphony) int t = (utilTimerTasksTail+1) & (UTILTIMERTASK_TASKS-1); while (t!=utilTimerTasksHead) { - if (UET_IS_BUFFER_WRITE_EVENT(utilTimerTasks[t].type)) + if (UET_IS_BUFFER_WRITE_EVENT(utilTimerTasks[t].type) && + utilTimerTasks[t].data.buffer.pinFunction == task->data.buffer.pinFunction) sum += ((int)(unsigned int)utilTimerTasks[t].data.buffer.currentValue) - 32768; t = (t+1) & (UTILTIMERTASK_TASKS-1); } diff --git a/src/jsutils.c b/src/jsutils.c index b6c2164f6..f6858c4c6 100644 --- a/src/jsutils.c +++ b/src/jsutils.c @@ -361,7 +361,16 @@ NO_INLINE void jsAssertFail(const char *file, int line, const char *expr) { jshTransmitFlush(); NVIC_SystemReset(); #elif defined(ESP8266) - jsiConsolePrint("REBOOTING!\n"); + // typically the Espruino console is over telnet, in which case nothing we do here will ever + // show up, so we instead jump through some hoops to print to UART + int os_printf_plus(const char *format, ...) __attribute__((format(printf, 1, 2))); + os_printf_plus("ASSERT FAILED AT %s:%d\n", file,line); + jsiConsolePrint("---console end---\n"); + int c, console = jsiGetConsoleDevice(); + while ((c=jshGetCharToTransmit(console)) >= 0) + os_printf_plus("%c", c); + os_printf_plus("CRASHING.\n"); + *(int*)0xdead = 0xbeef; extern void jswrap_ESP8266_reboot(void); jswrap_ESP8266_reboot(); while(1) ; diff --git a/src/jsvar.c b/src/jsvar.c index a45d3fd31..ce1f62cc2 100644 --- a/src/jsvar.c +++ b/src/jsvar.c @@ -1154,10 +1154,10 @@ JsVar *jsvAsString(JsVar *v, bool unlockVar) { // Function found and it's not the default one - execute it JsVar *result = jspExecuteFunction(toStringFn,v,0,0); jsvUnLock(toStringFn); - return jsvAsString(result, true); + str = jsvAsString(result, true); } else { jsvUnLock(toStringFn); - return jsvNewFromString("[object Object]"); + str = jsvNewFromString("[object Object]"); } } else { const char *constChar = jsvGetConstString(v); diff --git a/src/jsvariterator.c b/src/jsvariterator.c index c9df735fc..454cb5b85 100644 --- a/src/jsvariterator.c +++ b/src/jsvariterator.c @@ -238,6 +238,16 @@ void jsvStringIteratorAppend(JsvStringIterator *it, char ch) { jsvSetCharactersInVar(it->var, it->charsInVar); } +void jsvStringIteratorAppendString(JsvStringIterator *it, JsVar *str) { + JsvStringIterator sit; + jsvStringIteratorNew(&sit, str, 0); + while (jsvStringIteratorHasChar(&sit)) { + jsvStringIteratorAppend(it, jsvStringIteratorGetChar(&sit)); + jsvStringIteratorNext(&sit); + } + jsvStringIteratorFree(&sit); +} + // -------------------------------------------------------------------------------------------- void jsvObjectIteratorNew(JsvObjectIterator *it, JsVar *obj) { diff --git a/src/jsvariterator.h b/src/jsvariterator.h index 772a9fd05..ab401115c 100644 --- a/src/jsvariterator.h +++ b/src/jsvariterator.h @@ -105,6 +105,9 @@ void jsvStringIteratorGotoEnd(JsvStringIterator *it); /// Append a character TO THE END of a string iterator void jsvStringIteratorAppend(JsvStringIterator *it, char ch); +/// Append an entire JsVar string TO THE END of a string iterator +void jsvStringIteratorAppendString(JsvStringIterator *it, JsVar *str); + static ALWAYS_INLINE void jsvStringIteratorFree(JsvStringIterator *it) { jsvUnLock(it->var); } diff --git a/src/jswrap_espruino.c b/src/jswrap_espruino.c index 736c0b31d..6707ffd2e 100644 --- a/src/jswrap_espruino.c +++ b/src/jswrap_espruino.c @@ -61,7 +61,7 @@ Use the STM32's internal thermistor to work out the temperature. While this is implemented on Espruino boards, it may not be implemented on other devices. If so it'll return NaN. **Note:** This is not entirely accurate and varies by a few degrees from chip to chip. It measures the **die temperature**, so when connected to USB it could be reading 10 over degrees C above ambient temperature. When running from battery with `setDeepSleep(true)` it is much more accurate though. - */ +*/ /*JSON{ "type" : "staticmethod", diff --git a/src/jswrap_flash.c b/src/jswrap_flash.c index 3d644faa3..1d35d7b4b 100644 --- a/src/jswrap_flash.c +++ b/src/jswrap_flash.c @@ -523,6 +523,11 @@ bool jsfLoadBootCodeFromFlash(bool isReset) { if (isReset && !(bootCodeInfo & BOOT_CODE_RUN_ALWAYS)) return false; code = (char *)(FLASH_DATA_LOCATION); +#ifdef ESP8266 + // the flash address is just the offset into the flash chip, but to evaluate the code + // below we need to jump to the memory-mapped window onto flash, so adjust here + code += 0x40200000; +#endif #endif jsvUnLock(jspEvaluate(code, true /* We are expecting this ptr to hang around */)); return true; diff --git a/src/jswrap_io.c b/src/jswrap_io.c index 3a4136ccc..9f69a689b 100644 --- a/src/jswrap_io.c +++ b/src/jswrap_io.c @@ -345,6 +345,7 @@ Set the mode of the given pin. * `input_pulldown` - Digital input with internal ~40k pull-down resistor * `output` - Digital output * `opendrain` - Digital output that only ever pulls down to 0v. Sending a logical `1` leaves the pin open circuit + * `opendrain_pullup` - Digital output that pulls down to 0v. Sending a logical `1` enables internal ~40k pull-up resistor * `af_output` - Digital output from built-in peripheral * `af_opendrain` - Digital output from built-in peripheral that only ever pulls down to 0v. * Sending a logical `1` leaves the pin open circuit @@ -367,6 +368,7 @@ void jswrap_io_pinMode( else if (jsvIsStringEqual(mode, "input_pulldown")) m = JSHPINSTATE_GPIO_IN_PULLDOWN; else if (jsvIsStringEqual(mode, "output")) m = JSHPINSTATE_GPIO_OUT; else if (jsvIsStringEqual(mode, "opendrain")) m = JSHPINSTATE_GPIO_OUT_OPENDRAIN; + else if (jsvIsStringEqual(mode, "opendrain_pullup")) m = JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP; else if (jsvIsStringEqual(mode, "af_output")) m = JSHPINSTATE_AF_OUT; else if (jsvIsStringEqual(mode, "af_opendrain")) m = JSHPINSTATE_AF_OUT_OPENDRAIN; } @@ -391,7 +393,7 @@ void jswrap_io_pinMode( ], "return" : ["JsVar","The pin mode, as a string"] } -Return the current mode of the given pin. See `pinMode` for more information. +Return the current mode of the given pin. See `pinMode` for more information on returned values. */ JsVar *jswrap_io_getPinMode(Pin pin) { if (!jshIsPinValid(pin)) { @@ -407,6 +409,7 @@ JsVar *jswrap_io_getPinMode(Pin pin) { case JSHPINSTATE_GPIO_IN_PULLDOWN : text = "input_pulldown"; break; case JSHPINSTATE_GPIO_OUT : text = "output"; break; case JSHPINSTATE_GPIO_OUT_OPENDRAIN : text = "opendrain"; break; + case JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP : text = "opendrain_pullup"; break; case JSHPINSTATE_AF_OUT : text = "af_output"; break; case JSHPINSTATE_AF_OUT_OPENDRAIN : text = "af_opendrain"; break; default: break; diff --git a/src/jswrap_object.c b/src/jswrap_object.c index 8fd7b39ff..3030db765 100644 --- a/src/jswrap_object.c +++ b/src/jswrap_object.c @@ -172,6 +172,32 @@ Returns an array of all properties (enumerable or not) found directly on a given **Note:** This doesn't currently work as it should for built-in objects and their prototypes. See bug #380 */ + +void _jswrap_object_keys_or_property_names_iterator( + const JswSymList *symbols, + void (*callback)(void *data, JsVar *name), + void *data) { + if (!symbols) return; + unsigned int i; + unsigned char symbolCount = READ_FLASH_UINT8(&symbols->symbolCount); + for (i=0;isymbols[i].strOffset); +#ifndef USE_FLASH_MEMORY + JsVar *name = jsvNewFromString(&symbols->symbolChars[strOffset]); +#else + // On the esp8266 the string is in flash, so we have to copy it to RAM first + // We can't use flash_strncpy here because it assumes that strings start on a word + // boundary and that's not the case here. + char buf[64], *b = buf, c; const char *s = &symbols->symbolChars[strOffset]; + do { c = READ_FLASH_UINT8(s++); *b++ = c; } while (c && b != buf+64); + JsVar *name = jsvNewFromString(buf); +#endif + //os_printf_plus("OBJ cb %s\n", buf); + callback(data, name); + jsvUnLock(name); + } +} + /** This is for Object.keys and Object. However it uses a callback so doesn't allocate anything */ void jswrap_object_keys_or_property_names_cb( JsVar *obj, @@ -208,43 +234,32 @@ void jswrap_object_keys_or_property_names_cb( Assume that ALL builtins are non-enumerable. This isn't great but seems to work quite well right now! */ if (includeNonEnumerable) { - const JswSymList *symbols = 0; - JsVar *protoOwner = jspGetPrototypeOwner(obj); if (protoOwner) { // If protoOwner then this is the prototype (protoOwner is the object) - symbols = jswGetSymbolListForObjectProto(protoOwner); + const JswSymList *symbols = jswGetSymbolListForObjectProto(protoOwner); jsvUnLock(protoOwner); + _jswrap_object_keys_or_property_names_iterator(symbols, callback, data); } else if (!jsvIsObject(obj) || jsvIsRoot(obj)) { // get symbols, but only if we're not doing it on a basic object - symbols = jswGetSymbolListForObject(obj); + const JswSymList *symbols = jswGetSymbolListForObject(obj); + _jswrap_object_keys_or_property_names_iterator(symbols, callback, data); } - while (symbols) { - unsigned int i; - unsigned char symbolCount = READ_FLASH_UINT8(&symbols->symbolCount); - for (i=0;isymbols[i].strOffset); -#ifndef USE_FLASH_MEMORY - JsVar *name = jsvNewFromString(&symbols->symbolChars[strOffset]); -#else - // On the esp8266 the string is in flash, so we have to copy it to RAM first - // We can't use flash_strncpy here because it assumes that strings start on a word - // boundary and that's not the case here. - char buf[64], *b = buf, c; const char *s = &symbols->symbolChars[strOffset]; - do { c = READ_FLASH_UINT8(s++); *b++ = c; } while (c && b != buf+64); - JsVar *name = jsvNewFromString(buf); -#endif - //os_printf_plus("OBJ cb %s\n", buf); - callback(data, name); - jsvUnLock(name); - } - - symbols = 0; - if (includePrototype) { - includePrototype = false; - symbols = jswGetSymbolListForObjectProto(obj); + if (includePrototype) { + if (jsvIsObject(obj)) { + JsVar *proto = jsvObjectGetChild(obj, JSPARSE_INHERITS_VAR, 0); + while (jsvIsObject(proto)) { + const JswSymList *symbols = jswGetSymbolListForObjectProto(proto); + _jswrap_object_keys_or_property_names_iterator(symbols, callback, data); + JsVar *p2 = jsvObjectGetChild(proto, JSPARSE_INHERITS_VAR, 0); + jsvUnLock(proto); + proto = p2; + } } + // finally include Object/String/etc + const JswSymList *symbols = jswGetSymbolListForObjectProto(obj); + _jswrap_object_keys_or_property_names_iterator(symbols, callback, data); } if (jsvIsArray(obj) || jsvIsString(obj)) { @@ -622,7 +637,7 @@ void jswrap_object_emit(JsVar *parent, JsVar *event, JsVar *argArray) { jsWarn("First argument to EventEmitter.emit(..) must be a string"); return; } - JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event); + JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event); if (!eventName) return; // no memory // extract data @@ -678,7 +693,7 @@ void jswrap_object_removeListener(JsVar *parent, JsVar *event, JsVar *callback) } if (jsvIsString(event)) { // remove the whole child containing listeners - JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event); + JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event); if (!eventName) return; // no memory JsVar *eventListName = jsvFindChildFromVar(parent, eventName, true); jsvUnLock(eventName); @@ -722,7 +737,7 @@ void jswrap_object_removeAllListeners(JsVar *parent, JsVar *event) { } if (jsvIsString(event)) { // remove the whole child containing listeners - JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%s",event); + JsVar *eventName = jsvVarPrintf(JS_EVENT_PREFIX"%v", event); if (!eventName) return; // no memory JsVar *eventList = jsvFindChildFromVar(parent, eventName, true); diff --git a/src/jswrap_onewire.c b/src/jswrap_onewire.c index 837cfcb4c..377a28aef 100644 --- a/src/jswrap_onewire.c +++ b/src/jswrap_onewire.c @@ -31,7 +31,7 @@ static Pin onewire_getpin(JsVar *parent) { /** Reset one-wire, return true if a device was present */ static bool NO_INLINE OneWireReset(Pin pin) { - jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN); + jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP); //jshInterruptOff(); jshPinSetValue(pin, 0); jshDelayMicroseconds(500); @@ -45,7 +45,7 @@ static bool NO_INLINE OneWireReset(Pin pin) { /** Write 'bits' bits, and return what was read (to read, you must send all 1s) */ static JsVarInt NO_INLINE OneWireRead(Pin pin, int bits) { - jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN); + jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP); JsVarInt result = 0; JsVarInt mask = 1; while (bits-- > 0) { @@ -66,7 +66,7 @@ static JsVarInt NO_INLINE OneWireRead(Pin pin, int bits) { /** Write 'bits' bits, and return what was read (to read, you must send all 1s) */ static void NO_INLINE OneWireWrite(Pin pin, int bits, unsigned long long data) { - jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN); + jshPinSetState(pin, JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP); unsigned long long mask = 1; while (bits-- > 0) { if (data & mask) { // short pulse diff --git a/src/jswrap_promise.c b/src/jswrap_promise.c index fd5d12fc9..5a8d7b02f 100644 --- a/src/jswrap_promise.c +++ b/src/jswrap_promise.c @@ -24,6 +24,41 @@ #define JS_PROMISE_RESULT_NAME JS_HIDDEN_CHAR_STR"res" +/* + +var p = new Promise( function(resolve) { resolve(1); }); +p.then( function(value) { + console.log("A"+value); // 1 + return value + 1; +}).then( function(value) { + console.log(value); // 2 + return new Promise( function( resolve ) { resolve( 4 ); } ); +}).then( function( value ) { + console.log( value ); // 4 +} ); +p.then(function(value) { + console.log("B"+value); // 1 +}); + +produces: + +A1 +2 +4 + +Should produce + +A1 +B1 +2 +4 + +Basically .then should return a new promise, rather than returning the same one. + +_jswrap_promise_resolve should then execute every promise in the list. + + */ + /*JSON{ "type" : "class", "class" : "Promise", @@ -32,11 +67,73 @@ This is the built-in class for ES6 Promises */ -void _jswrap_promise_resolve(JsVar *promise, JsVar *data) { - JsVar *fn = jsvObjectGetChild(promise, JS_PROMISE_THEN_NAME, 0); - jsiExecuteEventCallback(promise, fn, 1, &data); +void _jswrap_promise_queueresolve(JsVar *promise, JsVar *data); +void _jswrap_promise_add(JsVar *parent, JsVar *callback, const char *name); +void _jswrap_promise_resolve_or_reject(JsVar *promise, JsVar *data, JsVar *fn) { + JsVar *result = 0; + if (jsvIsArray(fn)) { + JsvObjectIterator it; + jsvObjectIteratorNew(&it, fn); + bool first = true; + while (jsvObjectIteratorHasValue(&it)) { + JsVar *f = jsvObjectIteratorGetValue(&it); + JsVar *v = jspExecuteFunction(f, promise, 1, &data); + if (first) { + first = false; + result = v; + } else jsvUnLock(v); + jsvUnLock(f); + jsvObjectIteratorNext(&it); + } + jsvObjectIteratorFree(&it); + } else if (fn) { + result = jspExecuteFunction(fn, promise, 1, &data); + } + jsvObjectSetChild(promise, JS_PROMISE_THEN_NAME, 0); // remove 'resolve' and 'reject' handlers + jsvObjectSetChild(promise, JS_PROMISE_CATCH_NAME, 0); // remove 'resolve' and 'reject' handlers + JsVar *chainedPromise = jsvObjectGetChild(promise, "chain", 0); + jsvObjectSetChild(promise, "chain", 0); // unlink chain + if (chainedPromise) { + JsVar *constr = jspGetConstructor(result); + if (constr && (void*)constr->varData.native.ptr==(void*)jswrap_promise_constructor) { + // if we were given a promise, loop its 'then' in here + JsVar *fn = jsvNewNativeFunction((void (*)(void))_jswrap_promise_queueresolve, JSWAT_VOID|JSWAT_THIS_ARG|(JSWAT_JSVAR< 0.5) { - * printf("Too hot! (%f)", temperature.read()); - * } - * } - * } - * @endcode - */ -class AnalogIn { - -public: - - /** Create an AnalogIn, connected to the specified pin - * - * @param pin AnalogIn pin to connect to - * @param name (optional) A string to identify the object - */ - AnalogIn(PinName pin) { - analogin_init(&_adc, pin); - } - - /** Read the input voltage, represented as a float in the range [0.0, 1.0] - * - * @returns A floating-point value representing the current input voltage, measured as a percentage - */ - float read() { - return analogin_read(&_adc); - } - - /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF] - * - * @returns - * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value - */ - unsigned short read_u16() { - return analogin_read_u16(&_adc); - } - -#ifdef MBED_OPERATORS - /** An operator shorthand for read() - * - * The float() operator can be used as a shorthand for read() to simplify common code sequences - * - * Example: - * @code - * float x = volume.read(); - * float x = volume; - * - * if(volume.read() > 0.25) { ... } - * if(volume > 0.25) { ... } - * @endcode - */ - operator float() { - return read(); - } -#endif - -protected: - analogin_t _adc; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/AnalogOut.h b/targetlibs/libmbed/AnalogOut.h deleted file mode 100644 index 0b879a72b..000000000 --- a/targetlibs/libmbed/AnalogOut.h +++ /dev/null @@ -1,121 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ANALOGOUT_H -#define MBED_ANALOGOUT_H - -#include "platform.h" - -#if DEVICE_ANALOGOUT - -#include "analogout_api.h" - -namespace mbed { - -/** An analog output, used for setting the voltage on a pin - * - * Example: - * @code - * // Make a sawtooth output - * - * #include "mbed.h" - * - * AnalogOut tri(p18); - * int main() { - * while(1) { - * tri = tri + 0.01; - * wait_us(1); - * if(tri == 1) { - * tri = 0; - * } - * } - * } - * @endcode - */ -class AnalogOut { - -public: - - /** Create an AnalogOut connected to the specified pin - * - * @param AnalogOut pin to connect to (18) - */ - AnalogOut(PinName pin) { - analogout_init(&_dac, pin); - } - - /** Set the output voltage, specified as a percentage (float) - * - * @param value A floating-point value representing the output voltage, - * specified as a percentage. The value should lie between - * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%). - * Values outside this range will be saturated to 0.0f or 1.0f. - */ - void write(float value) { - analogout_write(&_dac, value); - } - - /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF] - * - * @param value 16-bit unsigned short representing the output voltage, - * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v) - */ - void write_u16(unsigned short value) { - analogout_write_u16(&_dac, value); - } - - /** Return the current output voltage setting, measured as a percentage (float) - * - * @returns - * A floating-point value representing the current voltage being output on the pin, - * measured as a percentage. The returned value will lie between - * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%). - * - * @note - * This value may not match exactly the value set by a previous write(). - */ - float read() { - return analogout_read(&_dac); - } - -#ifdef MBED_OPERATORS - /** An operator shorthand for write() - */ - AnalogOut& operator= (float percent) { - write(percent); - return *this; - } - - AnalogOut& operator= (AnalogOut& rhs) { - write(rhs.read()); - return *this; - } - - /** An operator shorthand for read() - */ - operator float() { - return read(); - } -#endif - -protected: - dac_t _dac; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/BusIn.h b/targetlibs/libmbed/BusIn.h deleted file mode 100644 index f6e760b0a..000000000 --- a/targetlibs/libmbed/BusIn.h +++ /dev/null @@ -1,67 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_BUSIN_H -#define MBED_BUSIN_H - -#include "platform.h" -#include "DigitalIn.h" - -namespace mbed { - -/** A digital input bus, used for reading the state of a collection of pins - */ -class BusIn { - -public: - /* Group: Configuration Methods */ - - /** Create an BusIn, connected to the specified pins - * - * @param DigitalIn pin to connect to bus bit (p5-p30, NC) - * - * @note - * It is only required to specify as many pin variables as is required - * for the bus; the rest will default to NC (not connected) - */ - BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, - PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, - PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, - PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); - - BusIn(PinName pins[16]); - - virtual ~BusIn(); - - /** Read the value of the input bus - * - * @returns - * An integer with each bit corresponding to the value read from the associated DigitalIn pin - */ - int read(); - -#ifdef MBED_OPERATORS - /** A shorthand for read() - */ - operator int(); -#endif - -protected: - DigitalIn* _pin[16]; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/BusInOut.h b/targetlibs/libmbed/BusInOut.h deleted file mode 100644 index 245fb411b..000000000 --- a/targetlibs/libmbed/BusInOut.h +++ /dev/null @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_BUSINOUT_H -#define MBED_BUSINOUT_H - -#include "DigitalInOut.h" - -namespace mbed { - -/** A digital input output bus, used for setting the state of a collection of pins - */ -class BusInOut { - -public: - - /** Create an BusInOut, connected to the specified pins - * - * @param p DigitalInOut pin to connect to bus bit p (p5-p30, NC) - * - * @note - * It is only required to specify as many pin variables as is required - * for the bus; the rest will default to NC (not connected) - */ - BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, - PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, - PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, - PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); - - BusInOut(PinName pins[16]); - - virtual ~BusInOut(); - - /* Group: Access Methods */ - - /** Write the value to the output bus - * - * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin - */ - void write(int value); - - - /** Read the value currently output on the bus - * - * @returns - * An integer with each bit corresponding to associated DigitalInOut pin setting - */ - int read(); - - /** Set as an output - */ - void output(); - - /** Set as an input - */ - void input(); - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone - */ - void mode(PinMode pull); - -#ifdef MBED_OPERATORS - /** A shorthand for write() - */ - BusInOut& operator= (int v); - BusInOut& operator= (BusInOut& rhs); - - /** A shorthand for read() - */ - operator int(); -#endif - -protected: - DigitalInOut* _pin[16]; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/BusOut.h b/targetlibs/libmbed/BusOut.h deleted file mode 100644 index f76c4a577..000000000 --- a/targetlibs/libmbed/BusOut.h +++ /dev/null @@ -1,76 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_BUSOUT_H -#define MBED_BUSOUT_H - -#include "DigitalOut.h" - -namespace mbed { - -/** A digital output bus, used for setting the state of a collection of pins - */ -class BusOut { - -public: - - /** Create an BusOut, connected to the specified pins - * - * @param p DigitalOut pin to connect to bus bit (p5-p30, NC) - * - * @note - * It is only required to specify as many pin variables as is required - * for the bus; the rest will default to NC (not connected) - */ - BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, - PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, - PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, - PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); - - BusOut(PinName pins[16]); - - virtual ~BusOut(); - - /** Write the value to the output bus - * - * @param value An integer specifying a bit to write for every corresponding DigitalOut pin - */ - void write(int value); - - /** Read the value currently output on the bus - * - * @returns - * An integer with each bit corresponding to associated DigitalOut pin setting - */ - int read(); - -#ifdef MBED_OPERATORS - /** A shorthand for write() - */ - BusOut& operator= (int v); - BusOut& operator= (BusOut& rhs); - - /** A shorthand for read() - */ - operator int(); -#endif - -protected: - DigitalOut* _pin[16]; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/CAN.h b/targetlibs/libmbed/CAN.h deleted file mode 100644 index af5501a2f..000000000 --- a/targetlibs/libmbed/CAN.h +++ /dev/null @@ -1,196 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_CAN_H -#define MBED_CAN_H - -#include "platform.h" - -#if DEVICE_CAN - -#include "can_api.h" -#include "can_helper.h" -#include "FunctionPointer.h" - -namespace mbed { - -/** CANMessage class - */ -class CANMessage : public CAN_Message { - -public: - /** Creates empty CAN message. - */ - CANMessage() { - len = 8; - type = CANData; - format = CANStandard; - id = 0; - memset(data, 0, 8); - } - - /** Creates CAN message with specific content. - */ - CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) { - len = _len & 0xF; - type = _type; - format = _format; - id = _id; - memcpy(data, _data, _len); - } - - /** Creates CAN remote message. - */ - CANMessage(int _id, CANFormat _format = CANStandard) { - len = 0; - type = CANRemote; - format = _format; - id = _id; - memset(data, 0, 8); - } -}; - -/** A can bus client, used for communicating with can devices - */ -class CAN { - -public: - /** Creates an CAN interface connected to specific pins. - * - * @param rd read from transmitter - * @param td transmit to transmitter - * - * Example: - * @code - * #include "mbed.h" - * - * Ticker ticker; - * DigitalOut led1(LED1); - * DigitalOut led2(LED2); - * CAN can1(p9, p10); - * CAN can2(p30, p29); - * - * char counter = 0; - * - * void send() { - * if(can1.write(CANMessage(1337, &counter, 1))) { - * printf("Message sent: %d\n", counter); - * counter++; - * } - * led1 = !led1; - * } - * - * int main() { - * ticker.attach(&send, 1); - * CANMessage msg; - * while(1) { - * if(can2.read(msg)) { - * printf("Message received: %d\n\n", msg.data[0]); - * led2 = !led2; - * } - * wait(0.2); - * } - * } - * @endcode - */ - CAN(PinName rd, PinName td); - virtual ~CAN(); - - /** Set the frequency of the CAN interface - * - * @param hz The bus frequency in hertz - * - * @returns - * 1 if successful, - * 0 otherwise - */ - int frequency(int hz); - - /** Write a CANMessage to the bus. - * - * @param msg The CANMessage to write. - * - * @returns - * 0 if write failed, - * 1 if write was successful - */ - int write(CANMessage msg); - - /** Read a CANMessage from the bus. - * - * @param msg A CANMessage to read to. - * - * @returns - * 0 if no message arrived, - * 1 if message arrived - */ - int read(CANMessage &msg); - - /** Reset CAN interface. - * - * To use after error overflow. - */ - void reset(); - - /** Puts or removes the CAN interface into silent monitoring mode - * - * @param silent boolean indicating whether to go into silent mode or not - */ - void monitor(bool silent); - - /** Returns number of read errors to detect read overflow errors. - */ - unsigned char rderror(); - - /** Returns number of write errors to detect write overflow errors. - */ - unsigned char tderror(); - - /** Attach a function to call whenever a CAN frame received interrupt is - * generated. - * - * @param fptr A pointer to a void function, or 0 to set as none - */ - void attach(void (*fptr)(void)); - - /** Attach a member function to call whenever a CAN frame received interrupt - * is generated. - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - */ - template - void attach(T* tptr, void (T::*mptr)(void)) { - if((mptr != NULL) && (tptr != NULL)) { - _rxirq.attach(tptr, mptr); - setup_interrupt(); - } else { - remove_interrupt(); - } - } - -private: - can_t _can; - FunctionPointer _rxirq; - - void setup_interrupt(void); - void remove_interrupt(void); -}; - -} // namespace mbed - -#endif - -#endif // MBED_CAN_H diff --git a/targetlibs/libmbed/DigitalIn.h b/targetlibs/libmbed/DigitalIn.h deleted file mode 100644 index 151a49ce3..000000000 --- a/targetlibs/libmbed/DigitalIn.h +++ /dev/null @@ -1,90 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DIGITALIN_H -#define MBED_DIGITALIN_H - -#include "platform.h" - -#include "gpio_api.h" - -namespace mbed { - -/** A digital input, used for reading the state of a pin - * - * Example: - * @code - * // Flash an LED while a DigitalIn is true - * - * #include "mbed.h" - * - * DigitalIn enable(p5); - * DigitalOut led(LED1); - * - * int main() { - * while(1) { - * if(enable) { - * led = !led; - * } - * wait(0.25); - * } - * } - * @endcode - */ -class DigitalIn { - -public: - /** Create a DigitalIn connected to the specified pin - * - * @param pin DigitalIn pin to connect to - * @param name (optional) A string to identify the object - */ - DigitalIn(PinName pin) { - gpio_init(&gpio, pin, PIN_INPUT); - } - - /** Read the input, represented as 0 or 1 (int) - * - * @returns - * An integer representing the state of the input pin, - * 0 for logical 0, 1 for logical 1 - */ - int read() { - return gpio_read(&gpio); - } - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone, OpenDrain - */ - void mode(PinMode pull) { - gpio_mode(&gpio, pull); - } - -#ifdef MBED_OPERATORS - /** An operator shorthand for read() - */ - operator int() { - return read(); - } -#endif - -protected: - gpio_t gpio; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/DigitalInOut.h b/targetlibs/libmbed/DigitalInOut.h deleted file mode 100644 index 72aee11bb..000000000 --- a/targetlibs/libmbed/DigitalInOut.h +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DIGITALINOUT_H -#define MBED_DIGITALINOUT_H - -#include "platform.h" - -#include "gpio_api.h" - -namespace mbed { - -/** A digital input/output, used for setting or reading a bi-directional pin - */ -class DigitalInOut { - -public: - /** Create a DigitalInOut connected to the specified pin - * - * @param pin DigitalInOut pin to connect to - */ - DigitalInOut(PinName pin) { - gpio_init(&gpio, pin, PIN_INPUT); - } - - /** Set the output, specified as 0 or 1 (int) - * - * @param value An integer specifying the pin output value, - * 0 for logical 0, 1 (or any other non-zero value) for logical 1 - */ - void write(int value) { - gpio_write(&gpio, value); - } - - /** Return the output setting, represented as 0 or 1 (int) - * - * @returns - * an integer representing the output setting of the pin if it is an output, - * or read the input if set as an input - */ - int read() { - return gpio_read(&gpio); - } - - /** Set as an output - */ - void output() { - gpio_dir(&gpio, PIN_OUTPUT); - } - - /** Set as an input - */ - void input() { - gpio_dir(&gpio, PIN_INPUT); - } - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone, OpenDrain - */ - void mode(PinMode pull) { - gpio_mode(&gpio, pull); - } - -#ifdef MBED_OPERATORS - /** A shorthand for write() - */ - DigitalInOut& operator= (int value) { - write(value); - return *this; - } - - DigitalInOut& operator= (DigitalInOut& rhs) { - write(rhs.read()); - return *this; - } - - /** A shorthand for read() - */ - operator int() { - return read(); - } -#endif - -protected: - gpio_t gpio; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/DigitalOut.h b/targetlibs/libmbed/DigitalOut.h deleted file mode 100644 index c8445e8ea..000000000 --- a/targetlibs/libmbed/DigitalOut.h +++ /dev/null @@ -1,97 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DIGITALOUT_H -#define MBED_DIGITALOUT_H - -#include "platform.h" -#include "gpio_api.h" - -namespace mbed { - -/** A digital output, used for setting the state of a pin - * - * Example: - * @code - * // Toggle a LED - * #include "mbed.h" - * - * DigitalOut led(LED1); - * - * int main() { - * while(1) { - * led = !led; - * wait(0.2); - * } - * } - * @endcode - */ -class DigitalOut { - -public: - /** Create a DigitalOut connected to the specified pin - * - * @param pin DigitalOut pin to connect to - */ - DigitalOut(PinName pin) { - gpio_init(&gpio, pin, PIN_OUTPUT); - } - - /** Set the output, specified as 0 or 1 (int) - * - * @param value An integer specifying the pin output value, - * 0 for logical 0, 1 (or any other non-zero value) for logical 1 - */ - void write(int value) { - gpio_write(&gpio, value); - } - - /** Return the output setting, represented as 0 or 1 (int) - * - * @returns - * an integer representing the output setting of the pin, - * 0 for logical 0, 1 for logical 1 - */ - int read() { - return gpio_read(&gpio); - } - -#ifdef MBED_OPERATORS - /** A shorthand for write() - */ - DigitalOut& operator= (int value) { - write(value); - return *this; - } - - DigitalOut& operator= (DigitalOut& rhs) { - write(rhs.read()); - return *this; - } - - /** A shorthand for read() - */ - operator int() { - return read(); - } -#endif - -protected: - gpio_t gpio; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/DirHandle.h b/targetlibs/libmbed/DirHandle.h deleted file mode 100644 index 329f4d1c7..000000000 --- a/targetlibs/libmbed/DirHandle.h +++ /dev/null @@ -1,104 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DIRHANDLE_H -#define MBED_DIRHANDLE_H - -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) -# define NAME_MAX 255 -typedef int mode_t; - -#else -# include -#endif - -#include "FileHandle.h" - -struct dirent { - char d_name[NAME_MAX+1]; -}; - -namespace mbed { - -/** Represents a directory stream. Objects of this type are returned - * by a FileSystemLike's opendir method. Implementations must define - * at least closedir, readdir and rewinddir. - * - * If a FileSystemLike class defines the opendir method, then the - * directories of an object of that type can be accessed by - * DIR *d = opendir("/example/directory") (or opendir("/example") - * to open the root of the filesystem), and then using readdir(d) etc. - * - * The root directory is considered to contain all FileLike and - * FileSystemLike objects, so the DIR* returned by opendir("/") will - * reflect this. - */ -class DirHandle { - -public: - /** Closes the directory. - * - * @returns - * 0 on success, - * -1 on error. - */ - virtual int closedir()=0; - - /** Return the directory entry at the current position, and - * advances the position to the next entry. - * - * @returns - * A pointer to a dirent structure representing the - * directory entry at the current position, or NULL on reaching - * end of directory or error. - */ - virtual struct dirent *readdir()=0; - - /** Resets the position to the beginning of the directory. - */ - virtual void rewinddir()=0; - - /** Returns the current position of the DirHandle. - * - * @returns - * the current position, - * -1 on error. - */ - virtual off_t telldir() { return -1; } - - /** Sets the position of the DirHandle. - * - * @param location The location to seek to. Must be a value returned by telldir. - */ - virtual void seekdir(off_t location) { } - - virtual ~DirHandle() {} -}; - -} // namespace mbed - -typedef mbed::DirHandle DIR; - -extern "C" { - DIR *opendir(const char*); - struct dirent *readdir(DIR *); - int closedir(DIR*); - void rewinddir(DIR*); - long telldir(DIR*); - void seekdir(DIR*, long); - int mkdir(const char *name, mode_t n); -}; - -#endif /* MBED_DIRHANDLE_H */ diff --git a/targetlibs/libmbed/Ethernet.h b/targetlibs/libmbed/Ethernet.h deleted file mode 100644 index 83a40b8f5..000000000 --- a/targetlibs/libmbed/Ethernet.h +++ /dev/null @@ -1,170 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ETHERNET_H -#define MBED_ETHERNET_H - -#include "platform.h" - -#if DEVICE_ETHERNET - -namespace mbed { - -/** An ethernet interface, to use with the ethernet pins. - * - * Example: - * @code - * // Read destination and source from every ethernet packet - * - * #include "mbed.h" - * - * Ethernet eth; - * - * int main() { - * char buf[0x600]; - * - * while(1) { - * int size = eth.receive(); - * if(size > 0) { - * eth.read(buf, size); - * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n", - * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n", - * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]); - * } - * - * wait(1); - * } - * } - * @endcode - */ -class Ethernet { - -public: - - /** Initialise the ethernet interface. - */ - Ethernet(); - - /** Powers the hardware down. - */ - virtual ~Ethernet(); - - enum Mode { - AutoNegotiate, - HalfDuplex10, - FullDuplex10, - HalfDuplex100, - FullDuplex100 - }; - - /** Writes into an outgoing ethernet packet. - * - * It will append size bytes of data to the previously written bytes. - * - * @param data An array to write. - * @param size The size of data. - * - * @returns - * The number of written bytes. - */ - int write(const char *data, int size); - - /** Send an outgoing ethernet packet. - * - * After filling in the data in an ethernet packet it must be send. - * Send will provide a new packet to write to. - * - * @returns - * 0 if the sending was failed, - * 1 if the package is successfully sent. - */ - int send(); - - /** Recevies an arrived ethernet packet. - * - * Receiving an ethernet packet will drop the last received ethernet packet - * and make a new ethernet packet ready to read. - * If no ethernet packet is arrived it will return 0. - * - * @returns - * 0 if no ethernet packet is arrived, - * or the size of the arrived packet. - */ - int receive(); - - /** Read from an recevied ethernet packet. - * - * After receive returnd a number bigger than 0it is - * possible to read bytes from this packet. - * Read will write up to size bytes into data. - * - * It is possible to use read multible times. - * Each time read will start reading after the last read byte before. - * - * @returns - * The number of byte read. - */ - int read(char *data, int size); - - /** Gives the ethernet address of the mbed. - * - * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in. - */ - void address(char *mac); - - /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up. - * - * @returns - * 0 if no ethernet link is pressent, - * 1 if an ethernet link is pressent. - * - * Example: - * @code - * // Using the Ethernet link function - * #include "mbed.h" - * - * Ethernet eth; - * - * int main() { - * wait(1); // Needed after startup. - * if (eth.link()) { - * printf("online\n"); - * } else { - * printf("offline\n"); - * } - * } - * @endcode - */ - int link(); - - /** Sets the speed and duplex parameters of an ethernet link - * - * - AutoNegotiate Auto negotiate speed and duplex - * - HalfDuplex10 10 Mbit, half duplex - * - FullDuplex10 10 Mbit, full duplex - * - HalfDuplex100 100 Mbit, half duplex - * - FullDuplex100 100 Mbit, full duplex - * - * @param mode the speed and duplex mode to set the link to: - */ - void set_link(Mode mode); -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/FileBase.h b/targetlibs/libmbed/FileBase.h deleted file mode 100644 index 86df2d1bc..000000000 --- a/targetlibs/libmbed/FileBase.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FILEBASE_H -#define MBED_FILEBASE_H - -typedef int FILEHANDLE; - -#include - -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) -# define O_RDONLY 0 -# define O_WRONLY 1 -# define O_RDWR 2 -# define O_CREAT 0x0200 -# define O_TRUNC 0x0400 -# define O_APPEND 0x0008 - -# define NAME_MAX 255 - -typedef int mode_t; -typedef int ssize_t; -typedef long off_t; - -#else -# include -# include -# include -#endif - -#include "platform.h" - -namespace mbed { - -typedef enum { - FilePathType, - FileSystemPathType -} PathType; - -class FileBase { -public: - FileBase(const char *name, PathType t); - - virtual ~FileBase(); - - const char* getName(void); - PathType getPathType(void); - - static FileBase *lookup(const char *name, unsigned int len); - - static FileBase *get(int n); - -protected: - static FileBase *_head; - - FileBase *_next; - const char *_name; - PathType _path_type; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/FileHandle.h b/targetlibs/libmbed/FileHandle.h deleted file mode 100644 index 0a98a827c..000000000 --- a/targetlibs/libmbed/FileHandle.h +++ /dev/null @@ -1,119 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FILEHANDLE_H -#define MBED_FILEHANDLE_H - -typedef int FILEHANDLE; - -#include - -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef int ssize_t; -typedef long off_t; - -#else -# include -#endif - -namespace mbed { - -/** An OO equivalent of the internal FILEHANDLE variable - * and associated _sys_* functions. - * - * FileHandle is an abstract class, needing at least sys_write and - * sys_read to be implmented for a simple interactive device. - * - * No one ever directly tals to/instanciates a FileHandle - it gets - * created by FileSystem, and wrapped up by stdio. - */ -class FileHandle { - -public: - /** Write the contents of a buffer to the file - * - * @param buffer the buffer to write from - * @param length the number of characters to write - * - * @returns - * The number of characters written (possibly 0) on success, -1 on error. - */ - virtual ssize_t write(const void* buffer, size_t length) = 0; - - /** Close the file - * - * @returns - * Zero on success, -1 on error. - */ - virtual int close() = 0; - - /** Function read - * Reads the contents of the file into a buffer - * - * @param buffer the buffer to read in to - * @param length the number of characters to read - * - * @returns - * The number of characters read (zero at end of file) on success, -1 on error. - */ - virtual ssize_t read(void* buffer, size_t length) = 0; - - /** Check if the handle is for a interactive terminal device. - * If so, line buffered behaviour is used by default - * - * @returns - * 1 if it is a terminal, - * 0 otherwise - */ - virtual int isatty() = 0; - - /** Move the file position to a given offset from a given location. - * - * @param offset The offset from whence to move to - * @param whence SEEK_SET for the start of the file, SEEK_CUR for the - * current file position, or SEEK_END for the end of the file. - * - * @returns - * new file position on success, - * -1 on failure or unsupported - */ - virtual off_t lseek(off_t offset, int whence) = 0; - - /** Flush any buffers associated with the FileHandle, ensuring it - * is up to date on disk - * - * @returns - * 0 on success or un-needed, - * -1 on error - */ - virtual int fsync() = 0; - - virtual off_t flen() { - /* remember our current position */ - off_t pos = lseek(0, SEEK_CUR); - if(pos == -1) return -1; - /* seek to the end to get the file length */ - off_t res = lseek(0, SEEK_END); - /* return to our old position */ - lseek(pos, SEEK_SET); - return res; - } - - virtual ~FileHandle(); -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/FileLike.h b/targetlibs/libmbed/FileLike.h deleted file mode 100644 index 666575c90..000000000 --- a/targetlibs/libmbed/FileLike.h +++ /dev/null @@ -1,44 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FILELIKE_H -#define MBED_FILELIKE_H - -#include "FileBase.h" -#include "FileHandle.h" - -namespace mbed { - -/* Class FileLike - * A file-like object is one that can be opened with fopen by - * fopen("/name", mode). It is intersection of the classes Base and - * FileHandle. - */ -class FileLike : public FileHandle, public FileBase { - -public: - /* Constructor FileLike - * - * Variables - * name - The name to use to open the file. - */ - FileLike(const char *name); - - virtual ~FileLike(); -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/FilePath.h b/targetlibs/libmbed/FilePath.h deleted file mode 100644 index 2e335bfeb..000000000 --- a/targetlibs/libmbed/FilePath.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FILEPATH_H -#define MBED_FILEPATH_H - -#include "platform.h" - -#include "FileSystemLike.h" -#include "FileLike.h" - -namespace mbed { - -class FilePath { -public: - FilePath(const char* file_path); - - const char* fileName(void); - - bool isFileSystem(void); - FileSystemLike* fileSystem(void); - - bool isFile(void); - FileLike* file(void); - -private: - const char* file_name; - FileBase* fb; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/FileSystemLike.h b/targetlibs/libmbed/FileSystemLike.h deleted file mode 100644 index 6680c4cb0..000000000 --- a/targetlibs/libmbed/FileSystemLike.h +++ /dev/null @@ -1,104 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FILESYSTEMLIKE_H -#define MBED_FILESYSTEMLIKE_H - -#include "platform.h" - -#include "FileBase.h" -#include "FileHandle.h" -#include "DirHandle.h" - -namespace mbed { - -/** A filesystem-like object is one that can be used to open files - * though it by fopen("/name/filename", mode) - * - * Implementations must define at least open (the default definitions - * of the rest of the functions just return error values). - */ -class FileSystemLike : public FileBase { - -public: - /** FileSystemLike constructor - * - * @param name The name to use for the filesystem. - */ - FileSystemLike(const char *name); - - virtual ~FileSystemLike(); - - static DirHandle *opendir(); - friend class BaseDirHandle; - - /** Opens a file from the filesystem - * - * @param filename The name of the file to open. - * @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with - * zero or more of O_CREAT, O_TRUNC, or O_APPEND. - * - * @returns - * A pointer to a FileHandle object representing the - * file on success, or NULL on failure. - */ - virtual FileHandle *open(const char *filename, int flags) = 0; - - /** Remove a file from the filesystem. - * - * @param filename the name of the file to remove. - * @param returns 0 on success, -1 on failure. - */ - virtual int remove(const char *filename) { return -1; }; - - /** Rename a file in the filesystem. - * - * @param oldname the name of the file to rename. - * @param newname the name to rename it to. - * - * @returns - * 0 on success, - * -1 on failure. - */ - virtual int rename(const char *oldname, const char *newname) { return -1; }; - - /** Opens a directory in the filesystem and returns a DirHandle - * representing the directory stream. - * - * @param name The name of the directory to open. - * - * @returns - * A DirHandle representing the directory stream, or - * NULL on failure. - */ - virtual DirHandle *opendir(const char *name) { return NULL; }; - - /** Creates a directory in the filesystem. - * - * @param name The name of the directory to create. - * @param mode The permissions to create the directory with. - * - * @returns - * 0 on success, - * -1 on failure. - */ - virtual int mkdir(const char *name, mode_t mode) { return -1; } - - // TODO other filesystem functions (mkdir, rm, rn, ls etc) -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/FunctionPointer.h b/targetlibs/libmbed/FunctionPointer.h deleted file mode 100644 index 6e3855c03..000000000 --- a/targetlibs/libmbed/FunctionPointer.h +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_FUNCTIONPOINTER_H -#define MBED_FUNCTIONPOINTER_H - -#include - -namespace mbed { - -/** A class for storing and calling a pointer to a static or member void function - */ -class FunctionPointer { -public: - - /** Create a FunctionPointer, attaching a static function - * - * @param function The void static function to attach (default is none) - */ - FunctionPointer(void (*function)(void) = 0); - - /** Create a FunctionPointer, attaching a member function - * - * @param object The object pointer to invoke the member function on (i.e. the this pointer) - * @param function The address of the void member function to attach - */ - template - FunctionPointer(T *object, void (T::*member)(void)) { - attach(object, member); - } - - /** Attach a static function - * - * @param function The void static function to attach (default is none) - */ - void attach(void (*function)(void) = 0); - - /** Attach a member function - * - * @param object The object pointer to invoke the member function on (i.e. the this pointer) - * @param function The address of the void member function to attach - */ - template - void attach(T *object, void (T::*member)(void)) { - _object = static_cast(object); - memcpy(_member, (char*)&member, sizeof(member)); - _membercaller = &FunctionPointer::membercaller; - _function = 0; - } - - /** Call the attached static or member function - */ - void call(); - -private: - template - static void membercaller(void *object, char *member) { - T* o = static_cast(object); - void (T::*m)(void); - memcpy((char*)&m, member, sizeof(m)); - (o->*m)(); - } - - void (*_function)(void); // static function pointer - 0 if none attached - void *_object; // object this pointer - 0 if none attached - char _member[16]; // raw member function pointer storage - converted back by registered _membercaller - void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/I2C.h b/targetlibs/libmbed/I2C.h deleted file mode 100644 index bd7cf1223..000000000 --- a/targetlibs/libmbed/I2C.h +++ /dev/null @@ -1,144 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_I2C_H -#define MBED_I2C_H - -#include "platform.h" - -#if DEVICE_I2C - -#include "i2c_api.h" - -namespace mbed { - -/** An I2C Master, used for communicating with I2C slave devices - * - * Example: - * @code - * // Read from I2C slave at address 0x62 - * - * #include "mbed.h" - * - * I2C i2c(p28, p27); - * - * int main() { - * int address = 0x62; - * char data[2]; - * i2c.read(address, data, 2); - * } - * @endcode - */ -class I2C { - -public: - enum RxStatus { - NoData, - MasterGeneralCall, - MasterWrite, - MasterRead - }; - - enum Acknowledge { - NoACK = 0, - ACK = 1 - }; - - /** Create an I2C Master interface, connected to the specified pins - * - * @param sda I2C data line pin - * @param scl I2C clock line pin - */ - I2C(PinName sda, PinName scl); - - /** Set the frequency of the I2C interface - * - * @param hz The bus frequency in hertz - */ - void frequency(int hz); - - /** Read from an I2C slave - * - * Performs a complete read transaction. The bottom bit of - * the address is forced to 1 to indicate a read. - * - * @param address 8-bit I2C slave address [ addr | 1 ] - * @param data Pointer to the byte-array to read data in to - * @param length Number of bytes to read - * @param repeated Repeated start, true - don't send stop at end - * - * @returns - * 0 on success (ack), - * non-0 on failure (nack) - */ - int read(int address, char *data, int length, bool repeated = false); - - /** Read a single byte from the I2C bus - * - * @param ack indicates if the byte is to be acknowledged (1 = acknowledge) - * - * @returns - * the byte read - */ - int read(int ack); - - /** Write to an I2C slave - * - * Performs a complete write transaction. The bottom bit of - * the address is forced to 0 to indicate a write. - * - * @param address 8-bit I2C slave address [ addr | 0 ] - * @param data Pointer to the byte-array data to send - * @param length Number of bytes to send - * @param repeated Repeated start, true - do not send stop at end - * - * @returns - * 0 on success (ack), - * non-0 on failure (nack) - */ - int write(int address, const char *data, int length, bool repeated = false); - - /** Write single byte out on the I2C bus - * - * @param data data to write out on bus - * - * @returns - * '1' if an ACK was received, - * '0' otherwise - */ - int write(int data); - - /** Creates a start condition on the I2C bus - */ - - void start(void); - - /** Creates a stop condition on the I2C bus - */ - void stop(void); - -protected: - void aquire(); - - i2c_t _i2c; - static I2C *_owner; - int _hz; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/I2CSlave.h b/targetlibs/libmbed/I2CSlave.h deleted file mode 100644 index 738faea27..000000000 --- a/targetlibs/libmbed/I2CSlave.h +++ /dev/null @@ -1,154 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_I2C_SLAVE_H -#define MBED_I2C_SLAVE_H - -#include "platform.h" - -#if DEVICE_I2CSLAVE - -#include "i2c_api.h" - -namespace mbed { - -/** An I2C Slave, used for communicating with an I2C Master device - * - * Example: - * @code - * // Simple I2C responder - * #include - * - * I2CSlave slave(p9, p10); - * - * int main() { - * char buf[10]; - * char msg[] = "Slave!"; - * - * slave.address(0xA0); - * while (1) { - * int i = slave.receive(); - * switch (i) { - * case I2CSlave::ReadAddressed: - * slave.write(msg, strlen(msg) + 1); // Includes null char - * break; - * case I2CSlave::WriteGeneral: - * slave.read(buf, 10); - * printf("Read G: %s\n", buf); - * break; - * case I2CSlave::WriteAddressed: - * slave.read(buf, 10); - * printf("Read A: %s\n", buf); - * break; - * } - * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer - * } - * } - * @endcode - */ -class I2CSlave { - -public: - enum RxStatus { - NoData = 0, - ReadAddressed = 1, - WriteGeneral = 2, - WriteAddressed = 3 - }; - - /** Create an I2C Slave interface, connected to the specified pins. - * - * @param sda I2C data line pin - * @param scl I2C clock line pin - */ - I2CSlave(PinName sda, PinName scl); - - /** Set the frequency of the I2C interface - * - * @param hz The bus frequency in hertz - */ - void frequency(int hz); - - /** Checks to see if this I2C Slave has been addressed. - * - * @returns - * A status indicating if the device has been addressed, and how - * - NoData - the slave has not been addressed - * - ReadAddressed - the master has requested a read from this slave - * - WriteAddressed - the master is writing to this slave - * - WriteGeneral - the master is writing to all slave - */ - int receive(void); - - /** Read from an I2C master. - * - * @param data pointer to the byte array to read data in to - * @param length maximum number of bytes to read - * - * @returns - * 0 on success, - * non-0 otherwise - */ - int read(char *data, int length); - - /** Read a single byte from an I2C master. - * - * @returns - * the byte read - */ - int read(void); - - /** Write to an I2C master. - * - * @param data pointer to the byte array to be transmitted - * @param length the number of bytes to transmite - * - * @returns - * 0 on success, - * non-0 otherwise - */ - int write(const char *data, int length); - - /** Write a single byte to an I2C master. - * - * @data the byte to write - * - * @returns - * '1' if an ACK was received, - * '0' otherwise - */ - int write(int data); - - /** Sets the I2C slave address. - * - * @param address The address to set for the slave (ignoring the least - * signifcant bit). If set to 0, the slave will only respond to the - * general call address. - */ - void address(int address); - - /** Reset the I2C slave back into the known ready receiving state. - */ - void stop(void); - -protected: - i2c_t _i2c; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/InterruptIn.h b/targetlibs/libmbed/InterruptIn.h deleted file mode 100644 index 2889ee14e..000000000 --- a/targetlibs/libmbed/InterruptIn.h +++ /dev/null @@ -1,126 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_INTERRUPTIN_H -#define MBED_INTERRUPTIN_H - -#include "platform.h" - -#if DEVICE_INTERRUPTIN - -#include "gpio_api.h" -#include "gpio_irq_api.h" - -#include "FunctionPointer.h" - -namespace mbed { - -/** A digital interrupt input, used to call a function on a rising or falling edge - * - * Example: - * @code - * // Flash an LED while waiting for events - * - * #include "mbed.h" - * - * InterruptIn event(p16); - * DigitalOut led(LED1); - * - * void trigger() { - * printf("triggered!\n"); - * } - * - * int main() { - * event.rise(&trigger); - * while(1) { - * led = !led; - * wait(0.25); - * } - * } - * @endcode - */ -class InterruptIn { - -public: - - /** Create an InterruptIn connected to the specified pin - * - * @param pin InterruptIn pin to connect to - * @param name (optional) A string to identify the object - */ - InterruptIn(PinName pin); - virtual ~InterruptIn(); - - int read(); -#ifdef MBED_OPERATORS - operator int(); - -#endif - - /** Attach a function to call when a rising edge occurs on the input - * - * @param fptr A pointer to a void function, or 0 to set as none - */ - void rise(void (*fptr)(void)); - - /** Attach a member function to call when a rising edge occurs on the input - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - */ - template - void rise(T* tptr, void (T::*mptr)(void)) { - _rise.attach(tptr, mptr); - gpio_irq_set(&gpio_irq, IRQ_RISE, 1); - } - - /** Attach a function to call when a falling edge occurs on the input - * - * @param fptr A pointer to a void function, or 0 to set as none - */ - void fall(void (*fptr)(void)); - - /** Attach a member function to call when a falling edge occurs on the input - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - */ - template - void fall(T* tptr, void (T::*mptr)(void)) { - _fall.attach(tptr, mptr); - gpio_irq_set(&gpio_irq, IRQ_FALL, 1); - } - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone - */ - void mode(PinMode pull); - - static void _irq_handler(uint32_t id, gpio_irq_event event); - -protected: - gpio_t gpio; - gpio_irq_t gpio_irq; - - FunctionPointer _rise; - FunctionPointer _fall; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/KL25Z/ARM/MKL25Z4.sct b/targetlibs/libmbed/KL25Z/ARM/MKL25Z4.sct deleted file mode 100644 index 769932467..000000000 --- a/targetlibs/libmbed/KL25Z/ARM/MKL25Z4.sct +++ /dev/null @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x20000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 0x4000 - 0xC0 = 0x3F40 - RW_IRAM1 0x1FFFF0C0 0x3F40 { - .ANY (+RW +ZI) - } -} - diff --git a/targetlibs/libmbed/KL25Z/ARM/mbed.ar b/targetlibs/libmbed/KL25Z/ARM/mbed.ar deleted file mode 100644 index ed5e5a816..000000000 Binary files a/targetlibs/libmbed/KL25Z/ARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/KL25Z/MKL25Z4.h b/targetlibs/libmbed/KL25Z/MKL25Z4.h deleted file mode 100644 index eec8402e5..000000000 --- a/targetlibs/libmbed/KL25Z/MKL25Z4.h +++ /dev/null @@ -1,4155 +0,0 @@ -/* -** ################################################################### -** Processor: MKL25Z128VLK4 -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL25RM, Rev.1, Jun 2012 -** Version: rev. 1.1, 2012-06-21 -** -** Abstract: -** CMSIS Peripheral Access Layer for MKL25Z4 -** -** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-06-13) -** Initial version. -** - rev. 1.1 (2012-06-21) -** Update according to reference manual rev. 1. -** -** ################################################################### -*/ - -/** - * @file MKL25Z4.h - * @version 1.1 - * @date 2012-06-21 - * @brief CMSIS Peripheral Access Layer for MKL25Z4 - * - * CMSIS Peripheral Access Layer for MKL25Z4 - */ - -#if !defined(MKL25Z4_H_) -#define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001u - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ - DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ - DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ - DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ - Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ - FTFA_IRQn = 5, /**< FTFA interrupt */ - LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 7, /**< Low Leakage Wakeup */ - I2C0_IRQn = 8, /**< I2C0 interrupt */ - I2C1_IRQn = 9, /**< I2C0 interrupt 25 */ - SPI0_IRQn = 10, /**< SPI0 interrupt */ - SPI1_IRQn = 11, /**< SPI1 interrupt */ - UART0_IRQn = 12, /**< UART0 status/error interrupt */ - UART1_IRQn = 13, /**< UART1 status/error interrupt */ - UART2_IRQn = 14, /**< UART2 status/error interrupt */ - ADC0_IRQn = 15, /**< ADC0 interrupt */ - CMP0_IRQn = 16, /**< CMP0 interrupt */ - TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */ - TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */ - TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */ - RTC_IRQn = 20, /**< RTC interrupt */ - RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */ - PIT_IRQn = 22, /**< PIT timer interrupt */ - Reserved39_IRQn = 23, /**< Reserved interrupt 39 */ - USB0_IRQn = 24, /**< USB0 interrupt */ - DAC0_IRQn = 25, /**< DAC interrupt */ - TSI0_IRQn = 26, /**< TSI0 interrupt */ - MCG_IRQn = 27, /**< MCG interrupt */ - LPTimer_IRQn = 28, /**< LPTimer interrupt */ - Reserved45_IRQn = 29, /**< Reserved interrupt 45 */ - PORTA_IRQn = 30, /**< Port A interrupt */ - PORTD_IRQn = 31 /**< Port D interrupt */ -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_MKL25Z4.h" /* Device specific configuration file */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ - uint8_t RESERVED_0[4]; - __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))< - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/targetlibs/libmbed/KL25Z/core_cmFunc.h b/targetlibs/libmbed/KL25Z/core_cmFunc.h deleted file mode 100644 index e42ceb161..000000000 --- a/targetlibs/libmbed/KL25Z/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.02 - * @date 24. May 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/targetlibs/libmbed/KL25Z/core_cmInstr.h b/targetlibs/libmbed/KL25Z/core_cmInstr.h deleted file mode 100644 index 33a84312d..000000000 --- a/targetlibs/libmbed/KL25Z/core_cmInstr.h +++ /dev/null @@ -1,643 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.03 - * @date 29. August 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/targetlibs/libmbed/KL25Z/device.h b/targetlibs/libmbed/KL25Z/device.h deleted file mode 100644 index 82374a022..000000000 --- a/targetlibs/libmbed/KL25Z/device.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif diff --git a/targetlibs/libmbed/KL25Z/gpio_object.h b/targetlibs/libmbed/KL25Z/gpio_object.h deleted file mode 100644 index 8f8d5eb59..000000000 --- a/targetlibs/libmbed/KL25Z/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/KL25Z/objects.h b/targetlibs/libmbed/KL25Z/objects.h deleted file mode 100644 index a5366deae..000000000 --- a/targetlibs/libmbed/KL25Z/objects.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - __IO uint32_t *MOD; - __IO uint32_t *CNT; - __IO uint32_t *CnV; -}; - -struct serial_s { - UARTLP_Type *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct dac_s { - DACName dac; -}; - -struct i2c_s { - I2C_Type *i2c; -}; - -struct spi_s { - SPI_Type *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/KL25Z/system_MKL25Z4.h b/targetlibs/libmbed/KL25Z/system_MKL25Z4.h deleted file mode 100644 index 908a2fbe1..000000000 --- a/targetlibs/libmbed/KL25Z/system_MKL25Z4.h +++ /dev/null @@ -1,84 +0,0 @@ -/* -** ################################################################### -** Processor: MKL25Z128VLK4 -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: KL25RM, Rev.1, Jun 2012 -** Version: rev. 1.1, 2012-06-21 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-06-13) -** Initial version. -** - rev. 1.1 (2012-06-21) -** Update according to reference manual rev. 1. -** -** ################################################################### -*/ - -/** - * @file MKL25Z4 - * @version 1.1 - * @date 2012-06-21 - * @brief Device specific configuration file for MKL25Z4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MKL25Z4_H_ -#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */ diff --git a/targetlibs/libmbed/LPC11U24/ARM/LPC11U24.sct b/targetlibs/libmbed/LPC11U24/ARM/LPC11U24.sct deleted file mode 100644 index c0378f732..000000000 --- a/targetlibs/libmbed/LPC11U24/ARM/LPC11U24.sct +++ /dev/null @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0xF40 - RW_IRAM1 0x100000C0 0xF40 { - .ANY (+RW +ZI) - } -} - diff --git a/targetlibs/libmbed/LPC11U24/ARM/mbed.ar b/targetlibs/libmbed/LPC11U24/ARM/mbed.ar deleted file mode 100644 index fcdeb9e9c..000000000 Binary files a/targetlibs/libmbed/LPC11U24/ARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/LPC11U24/LPC11Uxx.h b/targetlibs/libmbed/LPC11U24/LPC11Uxx.h deleted file mode 100644 index 7d2d24af3..000000000 --- a/targetlibs/libmbed/LPC11U24/LPC11Uxx.h +++ /dev/null @@ -1,670 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC11Uxx.h - * - * - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * default LPC11Uxx Device Series - * - * @version V0.1 - * @date 21. March 2011 - * - * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 - * - * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, - * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 - * - *******************************************************************************************************/ - -// ################################################################################ -// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000 -// ################################################################################ - -/** @addtogroup NXP - * @{ - */ - -/** @addtogroup LPC11Uxx - * @{ - */ - -#ifndef __LPC11UXX_H__ -#define __LPC11UXX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#if defined ( __CC_ARM ) - #pragma anon_unions -#endif - - /* Interrupt Number Definition */ - -typedef enum { -// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ -FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ - FLEX_INT1_IRQn = 1, - FLEX_INT2_IRQn = 2, - FLEX_INT3_IRQn = 3, - FLEX_INT4_IRQn = 4, - FLEX_INT5_IRQn = 5, - FLEX_INT6_IRQn = 6, - FLEX_INT7_IRQn = 7, - GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ - GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ - Reserved0_IRQn = 10, /*!< Reserved Interrupt */ - Reserved1_IRQn = 11, - Reserved2_IRQn = 12, - Reserved3_IRQn = 13, - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - USB_IRQn = 22, /*!< USB IRQ Interrupt */ - USB_FIQn = 23, /*!< USB FIQ Interrupt */ - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ - Reserved4_IRQn = 28, /*!< Reserved Interrupt */ - Reserved5_IRQn = 29, /*!< Reserved Interrupt */ - USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ - Reserved6_IRQn = 31, /*!< Reserved Interrupt */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ - -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) - */ - -typedef struct { /*!< (@ 0x40000000) I2C Structure */ - __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ - __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ - __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ - __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ - __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ - __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ - __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ - __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ - __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ - __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ - __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ - __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ -union{ - __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ - struct{ - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; - }; - }; -} LPC_I2C_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) - */ - -typedef struct { /*!< (@ 0x40004000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ - __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ - __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ - __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ - __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ - __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ -} LPC_WWDT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USART ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) - */ - -typedef struct { /*!< (@ 0x40008000) USART Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ - __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ - __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ - __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ - __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ - __I uint32_t RESERVED0[3]; - __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ - __I uint32_t RESERVED1; - __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ - __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; -} LPC_USART_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- Timer ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 - */ - -typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ - __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ - __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ - __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ - __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ - __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ - __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ - union { - __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ - struct{ - __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ - __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ - __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ - __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ - }; - }; - __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ - union{ - __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ - struct{ - __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ - __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ - __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ - __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ - }; - }; -__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ - __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ -} LPC_CTxxBx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) - */ - -typedef struct { /*!< (@ 0x4001C000) ADC Structure */ - __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ - __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ - __I uint32_t RESERVED0[1]; - __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ - union{ - __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ - struct{ - __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ - __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ - __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ - __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ - __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ - __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ - __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ - __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ - }; - }; - __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ -} LPC_ADC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- PMU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) - */ - -typedef struct { /*!< (@ 0x40038000) PMU Structure */ - __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ - union{ - __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ - struct{ - __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ - __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ - __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ - __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ - }; - }; -} LPC_PMU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- FLASHCTRL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) - */ - -typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ - __I uint32_t RESERVED2[1]; - __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ - __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ - __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ - __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ - __I uint32_t RESERVED3[1001]; - __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ - __I uint32_t RESERVED4[1]; - __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ -} LPC_FLASHCTRL_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) - */ - -typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ - __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ - __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ -} LPC_SSPx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- IOCONFIG ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ - __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ - __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ - __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ - __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ - __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ - __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ - __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ - __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ - __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ - __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ - __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ - __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ - __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ - __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ - __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ - __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ - __IO uint32_t PIO1_1; - __IO uint32_t PIO1_2; - __IO uint32_t PIO1_3; - __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ - __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ - __IO uint32_t PIO1_9; - __IO uint32_t PIO1_10; - __IO uint32_t PIO1_11; - __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ - __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ - __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ - __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ - __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ - __IO uint32_t PIO1_17; - __IO uint32_t PIO1_18; - __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ - __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ - __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ - __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ - __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ - __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ - __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ - __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ - __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ - __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ - __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ - __IO uint32_t PIO1_30; - __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ -} LPC_IOCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SYSCON ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) - */ - -typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ - __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ - __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ - __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ - __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ - __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ - __I uint32_t RESERVED0[2]; - __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ - __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ - __I uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ - __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ - __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ - __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ - __I uint32_t RESERVED3[8]; - __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ - __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ - __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ - __I uint32_t RESERVED4[1]; - __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ - __I uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ - __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ - __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ - __I uint32_t RESERVED6[8]; - __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ - __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ - __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ - __I uint32_t RESERVED7[5]; - __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ - __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ - __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ - __I uint32_t RESERVED8[5]; - __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ - __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ - __I uint32_t RESERVED9[18]; - __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ - __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ - __I uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ - __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ - __I uint32_t RESERVED11[25]; - __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ - __I uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ - __I uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ - __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ - __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ - __I uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ -} LPC_SYSCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) - */ - -typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ -} LPC_GPIO_PIN_INT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) - */ - -typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ - __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ -} LPC_GPIO_GROUP_INTx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- USB ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) - */ - -typedef struct { /*!< (@ 0x40080000) USB Structure */ - __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ - __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ - __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ - __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ - __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ - __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ - __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ - __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ - __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ - __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ - __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ - __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ - __I uint32_t RESERVED0[1]; - __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ -} LPC_USB_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - union { - struct { - __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ - __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ - }; - __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ - }; - __I uint32_t RESERVED0[1008]; - union { - struct { - __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ - __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ - }; - __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ - }; - uint32_t RESERVED1[960]; - __IO uint32_t DIR[2]; /* 0x2000 */ - uint32_t RESERVED2[30]; - __IO uint32_t MASK[2]; /* 0x2080 */ - uint32_t RESERVED3[30]; - __IO uint32_t PIN[2]; /* 0x2100 */ - uint32_t RESERVED4[30]; - __IO uint32_t MPIN[2]; /* 0x2180 */ - uint32_t RESERVED5[30]; - __IO uint32_t SET[2]; /* 0x2200 */ - uint32_t RESERVED6[30]; - __O uint32_t CLR[2]; /* 0x2280 */ - uint32_t RESERVED7[30]; - __O uint32_t NOT[2]; /* 0x2300 */ -} LPC_GPIO_Type; - - -#if defined ( __CC_ARM ) - #pragma no_anon_unions -#endif - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C_BASE (0x40000000) -#define LPC_WWDT_BASE (0x40004000) -#define LPC_USART_BASE (0x40008000) -#define LPC_CT16B0_BASE (0x4000C000) -#define LPC_CT16B1_BASE (0x40010000) -#define LPC_CT32B0_BASE (0x40014000) -#define LPC_CT32B1_BASE (0x40018000) -#define LPC_ADC_BASE (0x4001C000) -#define LPC_PMU_BASE (0x40038000) -#define LPC_FLASHCTRL_BASE (0x4003C000) -#define LPC_SSP0_BASE (0x40040000) -#define LPC_SSP1_BASE (0x40058000) -#define LPC_IOCON_BASE (0x40044000) -#define LPC_SYSCON_BASE (0x40048000) -#define LPC_GPIO_PIN_INT_BASE (0x4004C000) -#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) -#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) -#define LPC_USB_BASE (0x40080000) -#define LPC_GPIO_BASE (0x50000000) - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) -#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) -#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) -#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) -#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) -#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) -#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) -#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) -#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group (null) */ -/** @} */ /* End of group LPC11Uxx */ - -#ifdef __cplusplus -} -#endif - - -#endif // __LPC11UXX_H__ diff --git a/targetlibs/libmbed/LPC11U24/PeripheralNames.h b/targetlibs/libmbed/LPC11U24/PeripheralNames.h deleted file mode 100644 index 8fae2c63f..000000000 --- a/targetlibs/libmbed/LPC11U24/PeripheralNames.h +++ /dev/null @@ -1,71 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_USART_BASE -} UARTName; - -typedef enum { - I2C_0 = (int)LPC_I2C_BASE -} I2CName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC11U24/PinNames.h b/targetlibs/libmbed/LPC11U24/PinNames.h deleted file mode 100644 index 4e45c040b..000000000 --- a/targetlibs/libmbed/LPC11U24/PinNames.h +++ /dev/null @@ -1,165 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC11U Pin Names - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - - P1_0 = 32, - P1_1 = 33, - P1_2 = 34, - P1_3 = 35, - P1_4 = 36, - P1_5 = 37, - P1_6 = 38, - P1_7 = 39, - P1_8 = 40, - P1_9 = 41, - P1_10 = 42, - P1_11 = 43, - P1_12 = 44, - P1_13 = 45, - P1_14 = 46, - P1_15 = 47, - P1_16 = 48, - P1_17 = 49, - P1_18 = 50, - P1_19 = 51, - P1_20 = 52, - P1_21 = 53, - P1_22 = 54, - P1_23 = 55, - P1_24 = 56, - P1_25 = 57, - P1_26 = 58, - P1_27 = 59, - P1_28 = 60, - P1_29 = 61, - - P1_31 = 63, - - // mbed DIP Pin Names - p5 = P0_9, - p6 = P0_8, - p7 = P1_29, - p8 = P0_2, - p9 = P1_27, - p10 = P1_26, - p11 = P1_22, - p12 = P1_21, - p13 = P1_20, - p14 = P1_23, - p15 = P0_11, - p16 = P0_12, - p17 = P0_13, - p18 = P0_14, - p19 = P0_16, - p20 = P0_22, - p21 = P0_7, - p22 = P0_17, - p23 = P1_17, - p24 = P1_18, - p25 = P1_24, - p26 = P1_25, - p27 = P0_4, - p28 = P0_5, - p29 = P1_5, - p30 = P1_2, - - p33 = P0_3, - p34 = P1_15, - p35 = P0_20, - p36 = P0_21, - - // Other mbed Pin Names - LED1 = P1_8, - LED2 = P1_9, - LED3 = P1_10, - LED4 = P1_11, - - USBTX = P0_19, - USBRX = P0_18, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - CHANNEL0 = FLEX_INT0_IRQn, - CHANNEL1 = FLEX_INT1_IRQn, - CHANNEL2 = FLEX_INT2_IRQn, - CHANNEL3 = FLEX_INT3_IRQn, - CHANNEL4 = FLEX_INT4_IRQn, - CHANNEL5 = FLEX_INT5_IRQn, - CHANNEL6 = FLEX_INT6_IRQn, - CHANNEL7 = FLEX_INT7_IRQn -} Channel; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4 -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC11U24/PortNames.h b/targetlibs/libmbed/LPC11U24/PortNames.h deleted file mode 100644 index 3f272730a..000000000 --- a/targetlibs/libmbed/LPC11U24/PortNames.h +++ /dev/null @@ -1,31 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targetlibs/libmbed/LPC11U24/cmsis.h b/targetlibs/libmbed/LPC11U24/cmsis.h deleted file mode 100644 index 4e3857913..000000000 --- a/targetlibs/libmbed/LPC11U24/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC11Uxx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targetlibs/libmbed/LPC11U24/cmsis_nvic.h b/targetlibs/libmbed/LPC11U24/cmsis_nvic.h deleted file mode 100644 index 299d3879b..000000000 --- a/targetlibs/libmbed/LPC11U24/cmsis_nvic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC11U24/core_cm0.h b/targetlibs/libmbed/LPC11U24/core_cm0.h deleted file mode 100644 index 0feff0912..000000000 --- a/targetlibs/libmbed/LPC11U24/core_cm0.h +++ /dev/null @@ -1,667 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.02 - * @date 05. November 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/targetlibs/libmbed/LPC11U24/core_cmFunc.h b/targetlibs/libmbed/LPC11U24/core_cmFunc.h deleted file mode 100644 index e42ceb161..000000000 --- a/targetlibs/libmbed/LPC11U24/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.02 - * @date 24. May 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/targetlibs/libmbed/LPC11U24/core_cmInstr.h b/targetlibs/libmbed/LPC11U24/core_cmInstr.h deleted file mode 100644 index 33a84312d..000000000 --- a/targetlibs/libmbed/LPC11U24/core_cmInstr.h +++ /dev/null @@ -1,643 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.03 - * @date 29. August 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/targetlibs/libmbed/LPC11U24/device.h b/targetlibs/libmbed/LPC11U24/device.h deleted file mode 100644 index ab3d32380..000000000 --- a/targetlibs/libmbed/LPC11U24/device.h +++ /dev/null @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/targetlibs/libmbed/LPC11U24/gpio_object.h b/targetlibs/libmbed/LPC11U24/gpio_object.h deleted file mode 100644 index 8f8d5eb59..000000000 --- a/targetlibs/libmbed/LPC11U24/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC11U24/objects.h b/targetlibs/libmbed/LPC11U24/objects.h deleted file mode 100644 index 755e77311..000000000 --- a/targetlibs/libmbed/LPC11U24/objects.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_mpin; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PWMName pwm; -}; - -struct serial_s { - LPC_USART_Type *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct i2c_s { - LPC_I2C_Type *i2c; -}; - -struct spi_s { - LPC_SSPx_Type *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC11U24/power_api.h b/targetlibs/libmbed/LPC11U24/power_api.h deleted file mode 100644 index a2794cdaf..000000000 --- a/targetlibs/libmbed/LPC11U24/power_api.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $ - * Project: NXP LPC11Uxx software example - * - * Description: - * Power API Header File for NXP LPC11Uxx Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. -****************************************************************************/ -#ifndef __LPC11UXX_POWER_API_H__ -#define __LPC11UXX_POWER_API_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#define PWRROMD_PRESENT - -typedef struct _PWRD { - void (*set_pll)(unsigned int cmd[], unsigned int resp[]); - void (*set_power)(unsigned int cmd[], unsigned int resp[]); -} PWRD; - -typedef struct _ROM { -#ifdef USBROMD_PRESENT - const USB * pUSBD; -#else - const unsigned p_usbd; -#endif /* USBROMD_PRESENT */ - const unsigned p_clib; - const unsigned p_cand; -#ifdef PWRROMD_PRESENT - const PWRD * pPWRD; -#else - const unsigned p_pwrd; -#endif /* PWRROMD_PRESENT */ - const unsigned p_dev1; - const unsigned p_dev2; - const unsigned p_dev3; - const unsigned p_dev4; -} ROM; - -//PLL setup related definitions -#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified -#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified -#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified -#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified - -#define PLL_CMD_SUCCESS 0 //PLL setup successfully found -#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output) -#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified -#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions -#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup - -//power setup elated definitions -#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface) -#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation) -#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance) -#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance - -#define PARAM_CMD_SUCCESS 0 //power setting successfully found -#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz) -#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid) - -#define MAX_CLOCK_KHZ_PARAM 50000 - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC11UXX_POWER_API_H__ */ - diff --git a/targetlibs/libmbed/LPC11U24/system_LPC11Uxx.h b/targetlibs/libmbed/LPC11U24/system_LPC11Uxx.h deleted file mode 100644 index e490d17dc..000000000 --- a/targetlibs/libmbed/LPC11U24/system_LPC11Uxx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11Uxx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11Uxx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11Uxx_H -#define __SYSTEM_LPC11Uxx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11Uxx_H */ diff --git a/targetlibs/libmbed/LPC11U24/uARM/LPC11U24.sct b/targetlibs/libmbed/LPC11U24/uARM/LPC11U24.sct deleted file mode 100644 index c0378f732..000000000 --- a/targetlibs/libmbed/LPC11U24/uARM/LPC11U24.sct +++ /dev/null @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x8000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0xF40 - RW_IRAM1 0x100000C0 0xF40 { - .ANY (+RW +ZI) - } -} - diff --git a/targetlibs/libmbed/LPC11U24/uARM/mbed.ar b/targetlibs/libmbed/LPC11U24/uARM/mbed.ar deleted file mode 100644 index a05f61d77..000000000 Binary files a/targetlibs/libmbed/LPC11U24/uARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/ARM/LPC1768.sct b/targetlibs/libmbed/LPC1768/ARM/LPC1768.sct deleted file mode 100644 index 329b074f5..000000000 --- a/targetlibs/libmbed/LPC1768/ARM/LPC1768.sct +++ /dev/null @@ -1,22 +0,0 @@ - -LR_IROM1 0x00000000 0x80000 { ; load region size_region - ER_IROM1 0x00000000 0x80000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8 - ; 32KB - 0xC8 = 0x7F38 - RW_IRAM1 0x100000C8 0x7F38 { - .ANY (+RW +ZI) - } - RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM - .ANY (AHBSRAM0) - } - RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM - .ANY (AHBSRAM1) - } - RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM - .ANY (CANRAM) - } -} diff --git a/targetlibs/libmbed/LPC1768/ARM/mbed.ar b/targetlibs/libmbed/LPC1768/ARM/mbed.ar deleted file mode 100644 index bbba3007f..000000000 Binary files a/targetlibs/libmbed/LPC1768/ARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/GCC_ARM/LPC1768.ld b/targetlibs/libmbed/LPC1768/GCC_ARM/LPC1768.ld deleted file mode 100644 index a96ab7320..000000000 --- a/targetlibs/libmbed/LPC1768/GCC_ARM/LPC1768.ld +++ /dev/null @@ -1,149 +0,0 @@ -/* Linker script for mbed LPC1768 */ - -/* Linker script to configure memory regions. */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K - RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 - - USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K - ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targetlibs/libmbed/LPC1768/GCC_ARM/libmbed.a b/targetlibs/libmbed/LPC1768/GCC_ARM/libmbed.a deleted file mode 100644 index e0c537e8b..000000000 Binary files a/targetlibs/libmbed/LPC1768/GCC_ARM/libmbed.a and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/GCC_CR/LPC1768.ld b/targetlibs/libmbed/LPC1768/GCC_CR/LPC1768.ld deleted file mode 100644 index defd433f0..000000000 --- a/targetlibs/libmbed/LPC1768/GCC_CR/LPC1768.ld +++ /dev/null @@ -1,153 +0,0 @@ -/* mbed - LPC1768 linker script - * Based linker script generated by Code Red Technologies Red Suite 4.1 - */ -GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o) - -MEMORY -{ - /* Define each memory region */ - MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */ - RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */ - RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */ - -} - /* Define a symbol for the top of each memory region */ - __top_MFlash512 = 0x0 + 0x80000; - __top_RamLoc32 = 0x10000000 + 0x8000; - __top_RamAHB32 = 0x2007c000 + 0x8000; - -ENTRY(ResetISR) - -SECTIONS -{ - - /* MAIN TEXT SECTION */ - .text : ALIGN(4) - { - FILL(0xff) - KEEP(*(.isr_vector)) - - /* Global Section Table */ - . = ALIGN(4) ; - __section_table_start = .; - __data_section_table = .; - LONG(LOADADDR(.data)); - LONG( ADDR(.data)) ; - LONG( SIZEOF(.data)); - LONG(LOADADDR(.data_RAM2)); - LONG( ADDR(.data_RAM2)) ; - LONG( SIZEOF(.data_RAM2)); - __data_section_table_end = .; - __bss_section_table = .; - LONG( ADDR(.bss)); - LONG( SIZEOF(.bss)); - LONG( ADDR(.bss_RAM2)); - LONG( SIZEOF(.bss_RAM2)); - __bss_section_table_end = .; - __section_table_end = . ; - /* End of Global Section Table */ - - - *(.after_vectors*) - - *(.text*) - *(.rodata .rodata.*) - . = ALIGN(4); - - /* C++ constructors etc */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - KEEP(*(.fini)); - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - /* End C++ */ - } > MFlash512 - - /* - * for exception handling/unwind - some Newlib functions (in common - * with C++ and STDC++) use this. - */ - .ARM.extab : ALIGN(4) - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > MFlash512 - __exidx_start = .; - - .ARM.exidx : ALIGN(4) - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > MFlash512 - __exidx_end = .; - - _etext = .; - - - .data_RAM2 : ALIGN(4) - { - FILL(0xff) - *(.data.$RAM2*) - *(.data.$RamAHB32*) - . = ALIGN(4) ; - } > RamAHB32 AT>MFlash512 - - /* MAIN DATA SECTION */ - - .uninit_RESERVED : ALIGN(4) - { - KEEP(*(.bss.$RESERVED*)) - } > RamLoc32 - - .data : ALIGN(4) - { - FILL(0xff) - _data = .; - *(vtable) - *(.data*) - . = ALIGN(4) ; - _edata = .; - } > RamLoc32 AT>MFlash512 - - - .bss_RAM2 : ALIGN(4) - { - *(.bss.$RAM2*) - *(.bss.$RamAHB32*) - . = ALIGN(4) ; - } > RamAHB32 - - /* MAIN BSS SECTION */ - .bss : ALIGN(4) - { - _bss = .; - *(.bss*) - *(COMMON) - . = ALIGN(4) ; - _ebss = .; - PROVIDE(end = .); - } > RamLoc32 - - PROVIDE(_pvHeapStart = .); - PROVIDE(_vStackTop = __top_RamLoc32 - 0); -} diff --git a/targetlibs/libmbed/LPC1768/GCC_CR/libmbed.a b/targetlibs/libmbed/LPC1768/GCC_CR/libmbed.a deleted file mode 100644 index e0717ac52..000000000 Binary files a/targetlibs/libmbed/LPC1768/GCC_CR/libmbed.a and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/GCC_CS/LPC1768.ld b/targetlibs/libmbed/LPC1768/GCC_CS/LPC1768.ld deleted file mode 100644 index f12646f38..000000000 --- a/targetlibs/libmbed/LPC1768/GCC_CS/LPC1768.ld +++ /dev/null @@ -1,212 +0,0 @@ -/* Linker script for mbed LPC1768 - * - * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 - * BugURL:https://support.codesourcery.com/GNUToolchain/ - * - * Copyright 2007 CodeSourcery. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. */ -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -ENTRY(__cs3_reset_cortex_m) -SEARCH_DIR(.) - -/* -ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8 -ram LENGTH: 32KB - 0xC8 = 0x7F38 -*/ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K - - ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 - - ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K - ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K -} - -/* These force the linker to search for particular symbols from - * the start of the link process and thus ensure the user's - * overrides are picked up - */ -EXTERN(__cs3_reset_cortex_m) -EXTERN(__cs3_interrupt_vector_cortex_m) -EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) - -PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); -PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); -PROVIDE(__cs3_heap_start = _end); -PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); - -SECTIONS -{ - .text : - { - CREATE_OBJECT_SYMBOLS - __cs3_region_start_rom = .; - *(.cs3.region-head.rom) - __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; - *(.cs3.interrupt_vector) - /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); - *(.rom) - *(.rom.b) - - __cs3_reset = __cs3_reset_cortex_m; - *(.cs3.reset) - /* Make sure we pulled in some reset code. */ - ASSERT (. != __cs3_reset, "No reset code"); - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - *(.gnu.warning) - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - - *(.rodata .rodata.* .gnu.linkonce.r.*) - - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.gcc_except_table) - *(.eh_frame_hdr) - *(.eh_frame) - - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - __cs3_regions = .; - LONG (0) - LONG (__cs3_region_init_ram) - LONG (__cs3_region_start_ram) - LONG (__cs3_region_init_size_ram) - LONG (__cs3_region_zero_size_ram) - } - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >rom - __exidx_end = .; - .text.align : - { - . = ALIGN(8); - _etext = .; - } >rom - __cs3_region_size_rom = LENGTH(rom); - __cs3_region_num = 1; - - .data : - { - __cs3_region_start_ram = .; - *(.cs3.region-head.ram) - KEEP(*(.jcr)) - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - *(.ram) - . = ALIGN (8); - _edata = .; - } >ram AT>rom - .bss : - { - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - *(.ram.b) - . = ALIGN (8); - _end = .; - __end = .; - } >ram AT>rom - /* This used for USB RAM section */ - .usb_ram (NOLOAD): - { - *.o (USB_RAM) - } > ram2 - .heap (NOLOAD) : - { - *(.heap) - } >ram - .stack (__cs3_stack - __cs3_stack_size) (NOLOAD): - { - *(.stack) - _estack = .; - PROVIDE(estack = .); - } >ram - - __cs3_region_init_ram = LOADADDR (.data); - __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; - __cs3_region_zero_size_ram = _end - _edata; - __cs3_region_size_ram = LENGTH(ram); - __cs3_region_num = 1; - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } - .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) } -} diff --git a/targetlibs/libmbed/LPC1768/GCC_CS/libmbed.a b/targetlibs/libmbed/LPC1768/GCC_CS/libmbed.a deleted file mode 100644 index 745821693..000000000 Binary files a/targetlibs/libmbed/LPC1768/GCC_CS/libmbed.a and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/IAR/LPC17xx.icf b/targetlibs/libmbed/LPC1768/IAR/LPC17xx.icf deleted file mode 100644 index 92ee01e15..000000000 --- a/targetlibs/libmbed/LPC1768/IAR/LPC17xx.icf +++ /dev/null @@ -1,40 +0,0 @@ -/* [ROM] */ -define symbol __intvec_start__ = 0x00000000; -define symbol __region_ROM_start__ = 0x00000000; -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; -define symbol __region_ROM_end__ = 0x0007FFFF; - -/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8*/ -define symbol __NVIC_start__ = 0x10000000; -define symbol __NVIC_end__ = 0x100000C7; -define symbol __region_RAM_start__ = 0x100000C8; -define symbol __region_RAM_end__ = 0x1000FFDF; -define symbol _AHB_RAM_start__ = 0x2007C000; -define symbol _AHB_RAM_end__ = 0x20083FFF; - -/* Memory regions */ -define memory mem with size = 4G; - -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; -define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__]; - -/* Stack and Heap */ -define symbol __size_cstack__ = 0x800; -define symbol __size_heap__ = 0x800; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; - -initialize by copy with packing = zeros { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__intvec_start__ { section .intvec }; -place at address mem:0x2FC { section CRPKEY }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; -place in AHB_RAM_region { section USB_RAM }; -place in CRP_region { section .crp }; diff --git a/targetlibs/libmbed/LPC1768/IAR/mbed.a b/targetlibs/libmbed/LPC1768/IAR/mbed.a deleted file mode 100644 index b6894a7c4..000000000 Binary files a/targetlibs/libmbed/LPC1768/IAR/mbed.a and /dev/null differ diff --git a/targetlibs/libmbed/LPC1768/LPC17xx.h b/targetlibs/libmbed/LPC1768/LPC17xx.h deleted file mode 100644 index 8c4050b3a..000000000 --- a/targetlibs/libmbed/LPC1768/LPC17xx.h +++ /dev/null @@ -1,1035 +0,0 @@ -/**************************************************************************//** - * @file LPC17xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC17xx Device Series - * @version: V1.09 - * @date: 17. March 2010 - - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC17xx_H__ -#define __LPC17xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC17xx Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ - TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ - UART0_IRQn = 5, /*!< UART0 Interrupt */ - UART1_IRQn = 6, /*!< UART1 Interrupt */ - UART2_IRQn = 7, /*!< UART2 Interrupt */ - UART3_IRQn = 8, /*!< UART3 Interrupt */ - PWM1_IRQn = 9, /*!< PWM1 Interrupt */ - I2C0_IRQn = 10, /*!< I2C0 Interrupt */ - I2C1_IRQn = 11, /*!< I2C1 Interrupt */ - I2C2_IRQn = 12, /*!< I2C2 Interrupt */ - SPI_IRQn = 13, /*!< SPI Interrupt */ - SSP0_IRQn = 14, /*!< SSP0 Interrupt */ - SSP1_IRQn = 15, /*!< SSP1 Interrupt */ - PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 22, /*!< A/D Converter Interrupt */ - BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ - USB_IRQn = 24, /*!< USB Interrupt */ - CAN_IRQn = 25, /*!< CAN Interrupt */ - DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ - I2S_IRQn = 27, /*!< I2S Interrupt */ - ENET_IRQn = 28, /*!< Ethernet Interrupt */ - RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ - MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ - QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ - PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ - USBActivity_IRQn = 33, /* USB Activity interrupt */ - CANActivity_IRQn = 34, /* CAN Activity interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_LPC17xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ - uint32_t RESERVED0[31]; - __IO uint32_t PLL0CON; /* Clocking and Power Control */ - __IO uint32_t PLL0CFG; - __I uint32_t PLL0STAT; - __O uint32_t PLL0FEED; - uint32_t RESERVED1[4]; - __IO uint32_t PLL1CON; - __IO uint32_t PLL1CFG; - __I uint32_t PLL1STAT; - __O uint32_t PLL1FEED; - uint32_t RESERVED2[4]; - __IO uint32_t PCON; - __IO uint32_t PCONP; - uint32_t RESERVED3[15]; - __IO uint32_t CCLKCFG; - __IO uint32_t USBCLKCFG; - __IO uint32_t CLKSRCSEL; - __IO uint32_t CANSLEEPCLR; - __IO uint32_t CANWAKEFLAGS; - uint32_t RESERVED4[10]; - __IO uint32_t EXTINT; /* External Interrupts */ - uint32_t RESERVED5; - __IO uint32_t EXTMODE; - __IO uint32_t EXTPOLAR; - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /* Reset */ - uint32_t RESERVED7[7]; - __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ - __IO uint32_t IRCTRIM; /* Clock Dividers */ - __IO uint32_t PCLKSEL0; - __IO uint32_t PCLKSEL1; - uint32_t RESERVED8[4]; - __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - __IO uint32_t DMAREQSEL; - __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t PINSEL0; - __IO uint32_t PINSEL1; - __IO uint32_t PINSEL2; - __IO uint32_t PINSEL3; - __IO uint32_t PINSEL4; - __IO uint32_t PINSEL5; - __IO uint32_t PINSEL6; - __IO uint32_t PINSEL7; - __IO uint32_t PINSEL8; - __IO uint32_t PINSEL9; - __IO uint32_t PINSEL10; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE0; - __IO uint32_t PINMODE1; - __IO uint32_t PINMODE2; - __IO uint32_t PINMODE3; - __IO uint32_t PINMODE4; - __IO uint32_t PINMODE5; - __IO uint32_t PINMODE6; - __IO uint32_t PINMODE7; - __IO uint32_t PINMODE8; - __IO uint32_t PINMODE9; - __IO uint32_t PINMODE_OD0; - __IO uint32_t PINMODE_OD1; - __IO uint32_t PINMODE_OD2; - __IO uint32_t PINMODE_OD3; - __IO uint32_t PINMODE_OD4; - __IO uint32_t I2CPADCFG; -} LPC_PINCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t FIODIR; - struct { - __IO uint16_t FIODIRL; - __IO uint16_t FIODIRH; - }; - struct { - __IO uint8_t FIODIR0; - __IO uint8_t FIODIR1; - __IO uint8_t FIODIR2; - __IO uint8_t FIODIR3; - }; - }; - uint32_t RESERVED0[3]; - union { - __IO uint32_t FIOMASK; - struct { - __IO uint16_t FIOMASKL; - __IO uint16_t FIOMASKH; - }; - struct { - __IO uint8_t FIOMASK0; - __IO uint8_t FIOMASK1; - __IO uint8_t FIOMASK2; - __IO uint8_t FIOMASK3; - }; - }; - union { - __IO uint32_t FIOPIN; - struct { - __IO uint16_t FIOPINL; - __IO uint16_t FIOPINH; - }; - struct { - __IO uint8_t FIOPIN0; - __IO uint8_t FIOPIN1; - __IO uint8_t FIOPIN2; - __IO uint8_t FIOPIN3; - }; - }; - union { - __IO uint32_t FIOSET; - struct { - __IO uint16_t FIOSETL; - __IO uint16_t FIOSETH; - }; - struct { - __IO uint8_t FIOSET0; - __IO uint8_t FIOSET1; - __IO uint8_t FIOSET2; - __IO uint8_t FIOSET3; - }; - }; - union { - __O uint32_t FIOCLR; - struct { - __O uint16_t FIOCLRL; - __O uint16_t FIOCLRH; - }; - struct { - __O uint8_t FIOCLR0; - __O uint8_t FIOCLR1; - __O uint8_t FIOCLR2; - __O uint8_t FIOCLR3; - }; - }; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - uint32_t RESERVED0[2]; - __IO uint32_t EMR; - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - __I uint32_t CR2; - __I uint32_t CR3; - uint32_t RESERVED0; - __IO uint32_t MR4; - __IO uint32_t MR5; - __IO uint32_t MR6; - __IO uint32_t PCR; - __IO uint32_t LER; - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __IO uint32_t FIFOLVL; -} LPC_UART_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __I uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[39]; - __IO uint32_t FIFOLVL; -} LPC_UART0_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __I uint8_t LSR; - uint8_t RESERVED3[3]; - __I uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; - uint8_t RESERVED11[3]; - __IO uint32_t FIFOLVL; -} LPC_UART1_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -typedef struct -{ - __IO uint32_t SPCR; - __I uint32_t SPSR; - __IO uint32_t SPDR; - __IO uint32_t SPCCR; - uint32_t RESERVED0[3]; - __IO uint32_t SPINT; -} LPC_SPI_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t I2CONSET; - __I uint32_t I2STAT; - __IO uint32_t I2DAT; - __IO uint32_t I2ADR0; - __IO uint32_t I2SCLH; - __IO uint32_t I2SCLL; - __O uint32_t I2CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t I2ADR1; - __IO uint32_t I2ADR2; - __IO uint32_t I2ADR3; - __I uint32_t I2DATA_BUFFER; - __IO uint32_t I2MASK0; - __IO uint32_t I2MASK1; - __IO uint32_t I2MASK2; - __IO uint32_t I2MASK3; -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t I2SDAO; - __IO uint32_t I2SDAI; - __O uint32_t I2STXFIFO; - __I uint32_t I2SRXFIFO; - __I uint32_t I2SSTATE; - __IO uint32_t I2SDMA1; - __IO uint32_t I2SDMA2; - __IO uint32_t I2SIRQ; - __IO uint32_t I2STXRATE; - __IO uint32_t I2SRXRATE; - __IO uint32_t I2STXBITRATE; - __IO uint32_t I2SRXBITRATE; - __IO uint32_t I2STXMODE; - __IO uint32_t I2SRXMODE; -} LPC_I2S_TypeDef; - -/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ -typedef struct -{ - __IO uint32_t RICOMPVAL; - __IO uint32_t RIMASK; - __IO uint8_t RICTRL; - uint8_t RESERVED0[3]; - __IO uint32_t RICOUNTER; -} LPC_RIT_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[7]; - __IO uint8_t CCR; - uint8_t RESERVED1[3]; - __IO uint8_t CIIR; - uint8_t RESERVED2[3]; - __IO uint8_t AMR; - uint8_t RESERVED3[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED4[3]; - __IO uint8_t MIN; - uint8_t RESERVED5[3]; - __IO uint8_t HOUR; - uint8_t RESERVED6[3]; - __IO uint8_t DOM; - uint8_t RESERVED7[3]; - __IO uint8_t DOW; - uint8_t RESERVED8[3]; - __IO uint16_t DOY; - uint16_t RESERVED9; - __IO uint8_t MONTH; - uint8_t RESERVED10[3]; - __IO uint16_t YEAR; - uint16_t RESERVED11; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t RTC_AUXEN; - uint8_t RESERVED12[3]; - __IO uint8_t RTC_AUX; - uint8_t RESERVED13[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED14[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED15[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED16[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED18[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED19; - __IO uint8_t ALMON; - uint8_t RESERVED20[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED21; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t WDMOD; - uint8_t RESERVED0[3]; - __IO uint32_t WDTC; - __O uint8_t WDFEED; - uint8_t RESERVED1[3]; - __I uint32_t WDTV; - __IO uint32_t WDCLKSEL; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t ADCR; - __IO uint32_t ADGDR; - uint32_t RESERVED0; - __IO uint32_t ADINTEN; - __I uint32_t ADDR0; - __I uint32_t ADDR1; - __I uint32_t ADDR2; - __I uint32_t ADDR3; - __I uint32_t ADDR4; - __I uint32_t ADDR5; - __I uint32_t ADDR6; - __I uint32_t ADDR7; - __I uint32_t ADSTAT; - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t DACR; - __IO uint32_t DACCTRL; - __IO uint16_t DACCNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ -typedef struct -{ - __I uint32_t MCCON; - __O uint32_t MCCON_SET; - __O uint32_t MCCON_CLR; - __I uint32_t MCCAPCON; - __O uint32_t MCCAPCON_SET; - __O uint32_t MCCAPCON_CLR; - __IO uint32_t MCTIM0; - __IO uint32_t MCTIM1; - __IO uint32_t MCTIM2; - __IO uint32_t MCPER0; - __IO uint32_t MCPER1; - __IO uint32_t MCPER2; - __IO uint32_t MCPW0; - __IO uint32_t MCPW1; - __IO uint32_t MCPW2; - __IO uint32_t MCDEADTIME; - __IO uint32_t MCCCP; - __IO uint32_t MCCR0; - __IO uint32_t MCCR1; - __IO uint32_t MCCR2; - __I uint32_t MCINTEN; - __O uint32_t MCINTEN_SET; - __O uint32_t MCINTEN_CLR; - __I uint32_t MCCNTCON; - __O uint32_t MCCNTCON_SET; - __O uint32_t MCCNTCON_CLR; - __I uint32_t MCINTFLAG; - __O uint32_t MCINTFLAG_SET; - __O uint32_t MCINTFLAG_CLR; - __O uint32_t MCCAP_CLR; -} LPC_MCPWM_TypeDef; - -/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ -typedef struct -{ - __O uint32_t QEICON; - __I uint32_t QEISTAT; - __IO uint32_t QEICONF; - __I uint32_t QEIPOS; - __IO uint32_t QEIMAXPOS; - __IO uint32_t CMPOS0; - __IO uint32_t CMPOS1; - __IO uint32_t CMPOS2; - __I uint32_t INXCNT; - __IO uint32_t INXCMP; - __IO uint32_t QEILOAD; - __I uint32_t QEITIME; - __I uint32_t QEIVEL; - __I uint32_t QEICAP; - __IO uint32_t VELCOMP; - __IO uint32_t FILTER; - uint32_t RESERVED0[998]; - __O uint32_t QEIIEC; - __O uint32_t QEIIES; - __I uint32_t QEIINTSTAT; - __I uint32_t QEIIE; - __O uint32_t QEICLR; - __O uint32_t QEISET; -} LPC_QEI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - __IO uint32_t AFMR; - __IO uint32_t SFF_sa; - __IO uint32_t SFF_GRP_sa; - __IO uint32_t EFF_sa; - __IO uint32_t EFF_GRP_sa; - __IO uint32_t ENDofTable; - __I uint32_t LUTerrAd; - __I uint32_t LUTerr; - __IO uint32_t FCANIE; - __IO uint32_t FCANIC0; - __IO uint32_t FCANIC1; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t CANTxSR; - __I uint32_t CANRxSR; - __I uint32_t CANMSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - __IO uint32_t MOD; - __O uint32_t CMR; - __IO uint32_t GSR; - __I uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t BTR; - __IO uint32_t EWL; - __I uint32_t SR; - __IO uint32_t RFS; - __IO uint32_t RID; - __IO uint32_t RDA; - __IO uint32_t RDB; - __IO uint32_t TFI1; - __IO uint32_t TID1; - __IO uint32_t TDA1; - __IO uint32_t TDB1; - __IO uint32_t TFI2; - __IO uint32_t TID2; - __IO uint32_t TDA2; - __IO uint32_t TDB2; - __IO uint32_t TFI3; - __IO uint32_t TID3; - __IO uint32_t TDA3; - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t DMACIntStat; - __I uint32_t DMACIntTCStat; - __O uint32_t DMACIntTCClear; - __I uint32_t DMACIntErrStat; - __O uint32_t DMACIntErrClr; - __I uint32_t DMACRawIntTCStat; - __I uint32_t DMACRawIntErrStat; - __I uint32_t DMACEnbldChns; - __IO uint32_t DMACSoftBReq; - __IO uint32_t DMACSoftSReq; - __IO uint32_t DMACSoftLBReq; - __IO uint32_t DMACSoftLSReq; - __IO uint32_t DMACConfig; - __IO uint32_t DMACSync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t DMACCSrcAddr; - __IO uint32_t DMACCDestAddr; - __IO uint32_t DMACCLLI; - __IO uint32_t DMACCControl; - __IO uint32_t DMACCConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t HcRevision; /* USB Host Registers */ - __IO uint32_t HcControl; - __IO uint32_t HcCommandStatus; - __IO uint32_t HcInterruptStatus; - __IO uint32_t HcInterruptEnable; - __IO uint32_t HcInterruptDisable; - __IO uint32_t HcHCCA; - __I uint32_t HcPeriodCurrentED; - __IO uint32_t HcControlHeadED; - __IO uint32_t HcControlCurrentED; - __IO uint32_t HcBulkHeadED; - __IO uint32_t HcBulkCurrentED; - __I uint32_t HcDoneHead; - __IO uint32_t HcFmInterval; - __I uint32_t HcFmRemaining; - __I uint32_t HcFmNumber; - __IO uint32_t HcPeriodicStart; - __IO uint32_t HcLSTreshold; - __IO uint32_t HcRhDescriptorA; - __IO uint32_t HcRhDescriptorB; - __IO uint32_t HcRhStatus; - __IO uint32_t HcRhPortStatus1; - __IO uint32_t HcRhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ - __IO uint32_t OTGIntEn; - __O uint32_t OTGIntSet; - __O uint32_t OTGIntClr; - __IO uint32_t OTGStCtrl; - __IO uint32_t OTGTmr; - uint32_t RESERVED1[58]; - - __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t USBDevIntEn; - __O uint32_t USBDevIntClr; - __O uint32_t USBDevIntSet; - - __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ - __I uint32_t USBCmdData; - - __I uint32_t USBRxData; /* USB Device Transfer Registers */ - __O uint32_t USBTxData; - __I uint32_t USBRxPLen; - __O uint32_t USBTxPLen; - __IO uint32_t USBCtrl; - __O uint32_t USBDevIntPri; - - __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t USBEpIntEn; - __O uint32_t USBEpIntClr; - __O uint32_t USBEpIntSet; - __O uint32_t USBEpIntPri; - - __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t USBEpInd; - __IO uint32_t USBMaxPSize; - - __I uint32_t USBDMARSt; /* USB Device DMA Registers */ - __O uint32_t USBDMARClr; - __O uint32_t USBDMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t USBUDCAH; - __I uint32_t USBEpDMASt; - __O uint32_t USBEpDMAEn; - __O uint32_t USBEpDMADis; - __I uint32_t USBDMAIntSt; - __IO uint32_t USBDMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t USBEoTIntSt; - __O uint32_t USBEoTIntClr; - __O uint32_t USBEoTIntSet; - __I uint32_t USBNDDRIntSt; - __O uint32_t USBNDDRIntClr; - __O uint32_t USBNDDRIntSet; - __I uint32_t USBSysErrIntSt; - __O uint32_t USBSysErrIntClr; - __O uint32_t USBSysErrIntSet; - uint32_t RESERVED4[15]; - - union { - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_TX; - }; - __I uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[824]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __IO uint32_t RxFilterWoLStatus; - __IO uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_GPIO_BASE (0x2009C000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_APB1_BASE (0x40080000UL) -#define LPC_AHB_BASE (0x50000000UL) -#define LPC_CM3_BASE (0xE0000000UL) - -/* APB0 peripherals */ -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) -#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) -#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) -#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) -#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) -#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) - -/* APB1 peripherals */ -#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) -#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) -#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) -#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) -#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) -#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) -#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) -#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) -#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) -#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) -#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) -#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) - -/* AHB peripherals */ -#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) -#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) -#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) -#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) -#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) -#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) -#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) -#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) -#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) -#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) - -/* GPIOs */ -#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) -#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) -#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) -#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) -#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) -#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) -#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) -#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) -#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) -#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) -#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) -#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) -#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) -#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) -#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) -#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) -#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) -#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) -#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) -#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) -#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) -#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) -#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) -#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) -#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) -#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) -#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) -#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) -#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) -#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) -#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) -#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) -#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) -#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) -#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) -#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) -#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) -#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) -#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) - -#endif // __LPC17xx_H__ diff --git a/targetlibs/libmbed/LPC1768/PeripheralNames.h b/targetlibs/libmbed/LPC1768/PeripheralNames.h deleted file mode 100644 index bda583dca..000000000 --- a/targetlibs/libmbed/LPC1768/PeripheralNames.h +++ /dev/null @@ -1,80 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_UART0_BASE, - UART_1 = (int)LPC_UART1_BASE, - UART_2 = (int)LPC_UART2_BASE, - UART_3 = (int)LPC_UART3_BASE -} UARTName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - I2C_0 = (int)LPC_I2C0_BASE, - I2C_1 = (int)LPC_I2C1_BASE, - I2C_2 = (int)LPC_I2C2_BASE -} I2CName; - -typedef enum { - PWM_1 = 1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6 -} PWMName; - -typedef enum { - CAN_1 = (int)LPC_CAN1_BASE, - CAN_2 = (int)LPC_CAN2_BASE -} CANName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC1768/PinNames.h b/targetlibs/libmbed/LPC1768/PinNames.h deleted file mode 100644 index 340efd763..000000000 --- a/targetlibs/libmbed/LPC1768/PinNames.h +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC Pin Names - P0_0 = LPC_GPIO0_BASE, - P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, - P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, - P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, - P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, - P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, - - // mbed DIP Pin Names - p5 = P0_9, - p6 = P0_8, - p7 = P0_7, - p8 = P0_6, - p9 = P0_0, - p10 = P0_1, - p11 = P0_18, - p12 = P0_17, - p13 = P0_15, - p14 = P0_16, - p15 = P0_23, - p16 = P0_24, - p17 = P0_25, - p18 = P0_26, - p19 = P1_30, - p20 = P1_31, - p21 = P2_5, - p22 = P2_4, - p23 = P2_3, - p24 = P2_2, - p25 = P2_1, - p26 = P2_0, - p27 = P0_11, - p28 = P0_10, - p29 = P0_5, - p30 = P0_4, - - // Other mbed Pin Names -#ifdef MCB1700 - LED1 = P1_28, - LED2 = P1_29, - LED3 = P1_31, - LED4 = P2_2, -#else - LED1 = P1_18, - LED2 = P1_20, - LED3 = P1_21, - LED4 = P1_23, -#endif - USBTX = P0_2, - USBRX = P0_3, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullUp = 0, - PullDown = 3, - PullNone = 2, - OpenDrain = 4 -} PinMode; - -// version of PINCON_TypeDef using register arrays -typedef struct { - __IO uint32_t PINSEL[11]; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE[10]; - __IO uint32_t PINMODE_OD[5]; -} PINCONARRAY_TypeDef; - -#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC1768/PortNames.h b/targetlibs/libmbed/LPC1768/PortNames.h deleted file mode 100644 index 270cdeecb..000000000 --- a/targetlibs/libmbed/LPC1768/PortNames.h +++ /dev/null @@ -1,34 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port2 = 2, - Port3 = 3, - Port4 = 4 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targetlibs/libmbed/LPC1768/cmsis.h b/targetlibs/libmbed/LPC1768/cmsis.h deleted file mode 100644 index 2e51a087d..000000000 --- a/targetlibs/libmbed/LPC1768/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC1768 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC17xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targetlibs/libmbed/LPC1768/cmsis_nvic.h b/targetlibs/libmbed/LPC1768/cmsis_nvic.h deleted file mode 100644 index 299d3879b..000000000 --- a/targetlibs/libmbed/LPC1768/cmsis_nvic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC1768/core_cm3.h b/targetlibs/libmbed/LPC1768/core_cm3.h deleted file mode 100644 index 25cc2650f..000000000 --- a/targetlibs/libmbed/LPC1768/core_cm3.h +++ /dev/null @@ -1,1612 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.02 - * @date 16. July 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/targetlibs/libmbed/LPC1768/core_cmFunc.h b/targetlibs/libmbed/LPC1768/core_cmFunc.h deleted file mode 100644 index e42ceb161..000000000 --- a/targetlibs/libmbed/LPC1768/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.02 - * @date 24. May 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/targetlibs/libmbed/LPC1768/core_cmInstr.h b/targetlibs/libmbed/LPC1768/core_cmInstr.h deleted file mode 100644 index 33a84312d..000000000 --- a/targetlibs/libmbed/LPC1768/core_cmInstr.h +++ /dev/null @@ -1,643 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.03 - * @date 29. August 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/targetlibs/libmbed/LPC1768/device.h b/targetlibs/libmbed/LPC1768/device.h deleted file mode 100644 index 50bd1f980..000000000 --- a/targetlibs/libmbed/LPC1768/device.h +++ /dev/null @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 1 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 1 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 1 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/targetlibs/libmbed/LPC1768/gpio_object.h b/targetlibs/libmbed/LPC1768/gpio_object.h deleted file mode 100644 index 8f8d5eb59..000000000 --- a/targetlibs/libmbed/LPC1768/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC1768/objects.h b/targetlibs/libmbed/LPC1768/objects.h deleted file mode 100644 index 41d717adc..000000000 --- a/targetlibs/libmbed/LPC1768/objects.h +++ /dev/null @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - __IO uint32_t *MR; - PWMName pwm; -}; - -struct serial_s { - LPC_UART_TypeDef *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct dac_s { - DACName dac; -}; - -struct can_s { - LPC_CAN_TypeDef *dev; -}; - -struct i2c_s { - LPC_I2C_TypeDef *i2c; -}; - -struct spi_s { - LPC_SSP_TypeDef *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC1768/system_LPC17xx.h b/targetlibs/libmbed/LPC1768/system_LPC17xx.h deleted file mode 100644 index 1f7a47def..000000000 --- a/targetlibs/libmbed/LPC1768/system_LPC17xx.h +++ /dev/null @@ -1,60 +0,0 @@ -/****************************************************************************** - * @file: system_LPC17xx.h - * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series - * @version: V1.02 - * @date: 27. July 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC17xx_H -#define __SYSTEM_LPC17xx_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC17xx_H */ diff --git a/targetlibs/libmbed/LPC2368/ARM/LPC2368.sct b/targetlibs/libmbed/LPC2368/ARM/LPC2368.sct deleted file mode 100644 index 9123cca13..000000000 --- a/targetlibs/libmbed/LPC2368/ARM/LPC2368.sct +++ /dev/null @@ -1,24 +0,0 @@ - -LR_IROM1 0x00000000 0x80000 { ; load region size_region - ER_IROM1 0x00000000 0x80000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x40000120 0x7EE0 { ; RW data, inc space for realmonitor - .ANY (+RW +ZI) - } - RW_IRAM2 0x7FD00000 0x2000 { ; RW data, USB RAM - .ANY (AHBSRAM0) - } - RW_IRAM3 0x7FE00000 0x4000 { ; RW data, ETH RAM - .ANY (AHBSRAM1) - } - RW_IRAM4 0xE0038000 0x0800 { ; RW data, CAN RAM - .ANY (CANRAM) - } - RW_IRAM5 0xE0084000 0x0800 { ; RW data, RTC RAM - .ANY (RTCRAM) - } -} - diff --git a/targetlibs/libmbed/LPC2368/ARM/mbed.ar b/targetlibs/libmbed/LPC2368/ARM/mbed.ar deleted file mode 100644 index 9caf99bac..000000000 Binary files a/targetlibs/libmbed/LPC2368/ARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/LPC2368/LPC23xx.h b/targetlibs/libmbed/LPC2368/LPC23xx.h deleted file mode 100644 index 4017a5445..000000000 --- a/targetlibs/libmbed/LPC2368/LPC23xx.h +++ /dev/null @@ -1,864 +0,0 @@ -/* mbed Microcontroller Library - LPC23xx CMSIS-like structs - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h - */ - -#ifndef __LPC23xx_H -#define __LPC23xx_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** LPC23xx Specific Interrupt Numbers *******************************************************/ - WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ - - TIMER0_IRQn = 4, /*!< Timer0 Interrupt */ - TIMER1_IRQn = 5, /*!< Timer1 Interrupt */ - UART0_IRQn = 6, /*!< UART0 Interrupt */ - UART1_IRQn = 7, /*!< UART1 Interrupt */ - PWM1_IRQn = 8, /*!< PWM1 Interrupt */ - I2C0_IRQn = 9, /*!< I2C0 Interrupt */ - SPI_IRQn = 10, /*!< SPI Interrupt */ - SSP0_IRQn = 10, /*!< SSP0 Interrupt */ - SSP1_IRQn = 11, /*!< SSP1 Interrupt */ - PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */ - RTC_IRQn = 13, /*!< Real Time Clock Interrupt */ - EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */ - EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */ - EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */ - EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */ - ADC_IRQn = 18, /*!< A/D Converter Interrupt */ - I2C1_IRQn = 19, /*!< I2C1 Interrupt */ - BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */ - ENET_IRQn = 21, /*!< Ethernet Interrupt */ - USB_IRQn = 22, /*!< USB Interrupt */ - CAN_IRQn = 23, /*!< CAN Interrupt */ - MIC_IRQn = 24, /*!< Multimedia Interface Controler */ - DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */ - TIMER2_IRQn = 26, /*!< Timer2 Interrupt */ - TIMER3_IRQn = 27, /*!< Timer3 Interrupt */ - UART2_IRQn = 28, /*!< UART2 Interrupt */ - UART3_IRQn = 29, /*!< UART3 Interrupt */ - I2C2_IRQn = 30, /*!< I2C2 Interrupt */ - I2S_IRQn = 31, /*!< I2S Interrupt */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the ARM7 Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include -#include "system_LPC23xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ -#if defined ( __CC_ARM ) - #pragma anon_unions -#endif - -/*------------- Vector Interupt Controler (VIC) ------------------------------*/ -typedef struct -{ - __I uint32_t IRQStatus; - __I uint32_t FIQStatus; - __I uint32_t RawIntr; - __IO uint32_t IntSelect; - __IO uint32_t IntEnable; - __O uint32_t IntEnClr; - __IO uint32_t SoftInt; - __O uint32_t SoftIntClr; - __IO uint32_t Protection; - __IO uint32_t SWPriorityMask; - __IO uint32_t RESERVED0[54]; - __IO uint32_t VectAddr[32]; - __IO uint32_t RESERVED1[32]; - __IO uint32_t VectPriority[32]; - __IO uint32_t RESERVED2[800]; - __IO uint32_t Address; -} LPC_VIC_TypeDef; - -/*------------- System Control (SC) ------------------------------------------*/ -typedef struct -{ - __IO uint32_t MAMCR; - __IO uint32_t MAMTIM; - uint32_t RESERVED0[14]; - __IO uint32_t MEMMAP; - uint32_t RESERVED1[15]; - __IO uint32_t PLL0CON; /* Clocking and Power Control */ - __IO uint32_t PLL0CFG; - __I uint32_t PLL0STAT; - __O uint32_t PLL0FEED; - uint32_t RESERVED2[12]; - __IO uint32_t PCON; - __IO uint32_t PCONP; - uint32_t RESERVED3[15]; - __IO uint32_t CCLKCFG; - __IO uint32_t USBCLKCFG; - __IO uint32_t CLKSRCSEL; - uint32_t RESERVED4[12]; - __IO uint32_t EXTINT; /* External Interrupts */ - __IO uint32_t INTWAKE; - __IO uint32_t EXTMODE; - __IO uint32_t EXTPOLAR; - uint32_t RESERVED6[12]; - __IO uint32_t RSID; /* Reset */ - __IO uint32_t CSPR; - __IO uint32_t AHBCFG1; - __IO uint32_t AHBCFG2; - uint32_t RESERVED7[4]; - __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ - __IO uint32_t IRCTRIM; /* Clock Dividers */ - __IO uint32_t PCLKSEL0; - __IO uint32_t PCLKSEL1; - uint32_t RESERVED8[4]; - __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ - uint32_t RESERVED9; -// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ - } LPC_SC_TypeDef; - -/*------------- Pin Connect Block (PINCON) -----------------------------------*/ -typedef struct -{ - __IO uint32_t PINSEL0; - __IO uint32_t PINSEL1; - __IO uint32_t PINSEL2; - __IO uint32_t PINSEL3; - __IO uint32_t PINSEL4; - __IO uint32_t PINSEL5; - __IO uint32_t PINSEL6; - __IO uint32_t PINSEL7; - __IO uint32_t PINSEL8; - __IO uint32_t PINSEL9; - __IO uint32_t PINSEL10; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE0; - __IO uint32_t PINMODE1; - __IO uint32_t PINMODE2; - __IO uint32_t PINMODE3; - __IO uint32_t PINMODE4; - __IO uint32_t PINMODE5; - __IO uint32_t PINMODE6; - __IO uint32_t PINMODE7; - __IO uint32_t PINMODE8; - __IO uint32_t PINMODE9; - __IO uint32_t PINMODE_OD0; - __IO uint32_t PINMODE_OD1; - __IO uint32_t PINMODE_OD2; - __IO uint32_t PINMODE_OD3; - __IO uint32_t PINMODE_OD4; -} LPC_PINCON_TypeDef; - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - __IO uint32_t FIODIR; - uint32_t RESERVED0[3]; - __IO uint32_t FIOMASK; - __IO uint32_t FIOPIN; - __IO uint32_t FIOSET; - __O uint32_t FIOCLR; -} LPC_GPIO_TypeDef; - -typedef struct -{ - __I uint32_t IntStatus; - __I uint32_t IO0IntStatR; - __I uint32_t IO0IntStatF; - __O uint32_t IO0IntClr; - __IO uint32_t IO0IntEnR; - __IO uint32_t IO0IntEnF; - uint32_t RESERVED0[3]; - __I uint32_t IO2IntStatR; - __I uint32_t IO2IntStatF; - __O uint32_t IO2IntClr; - __IO uint32_t IO2IntEnR; - __IO uint32_t IO2IntEnF; -} LPC_GPIOINT_TypeDef; - -/*------------- Timer (TIM) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - uint32_t RESERVED0[2]; - __IO uint32_t EMR; - uint32_t RESERVED1[12]; - __IO uint32_t CTCR; -} LPC_TIM_TypeDef; - -/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - __I uint32_t CR1; - __I uint32_t CR2; - __I uint32_t CR3; - uint32_t RESERVED0; - __IO uint32_t MR4; - __IO uint32_t MR5; - __IO uint32_t MR6; - __IO uint32_t PCR; - __IO uint32_t LER; - uint32_t RESERVED1[7]; - __IO uint32_t CTCR; -} LPC_PWM_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[7]; - __IO uint8_t LSR; - uint8_t RESERVED2[7]; - __IO uint8_t SCR; - uint8_t RESERVED3[3]; - __IO uint32_t ACR; - __IO uint8_t ICR; - uint8_t RESERVED4[3]; - __IO uint8_t FDR; - uint8_t RESERVED5[7]; - __IO uint8_t TER; - uint8_t RESERVED6[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED7[3]; - __IO uint8_t ADRMATCH; -} LPC_UART_TypeDef; - -typedef struct -{ - union { - __I uint8_t RBR; - __O uint8_t THR; - __IO uint8_t DLL; - uint32_t RESERVED0; - }; - union { - __IO uint8_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint8_t FCR; - }; - __IO uint8_t LCR; - uint8_t RESERVED1[3]; - __IO uint8_t MCR; - uint8_t RESERVED2[3]; - __IO uint8_t LSR; - uint8_t RESERVED3[3]; - __IO uint8_t MSR; - uint8_t RESERVED4[3]; - __IO uint8_t SCR; - uint8_t RESERVED5[3]; - __IO uint32_t ACR; - uint32_t RESERVED6; - __IO uint32_t FDR; - uint32_t RESERVED7; - __IO uint8_t TER; - uint8_t RESERVED8[27]; - __IO uint8_t RS485CTRL; - uint8_t RESERVED9[3]; - __IO uint8_t ADRMATCH; - uint8_t RESERVED10[3]; - __IO uint8_t RS485DLY; -} LPC_UART1_TypeDef; - -/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ -typedef struct -{ - __IO uint32_t SPCR; - __I uint32_t SPSR; - __IO uint32_t SPDR; - __IO uint32_t SPCCR; - uint32_t RESERVED0[3]; - __IO uint32_t SPINT; -} LPC_SPI_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; - __IO uint32_t DMACR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t I2CONSET; - __I uint32_t I2STAT; - __IO uint32_t I2DAT; - __IO uint32_t I2ADR0; - __IO uint32_t I2SCLH; - __IO uint32_t I2SCLL; - __O uint32_t I2CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t I2ADR1; - __IO uint32_t I2ADR2; - __IO uint32_t I2ADR3; - __I uint32_t I2DATA_BUFFER; - __IO uint32_t I2MASK0; - __IO uint32_t I2MASK1; - __IO uint32_t I2MASK2; - __IO uint32_t I2MASK3; -} LPC_I2C_TypeDef; - -/*------------- Inter IC Sound (I2S) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t I2SDAO; - __I uint32_t I2SDAI; - __O uint32_t I2STXFIFO; - __I uint32_t I2SRXFIFO; - __I uint32_t I2SSTATE; - __IO uint32_t I2SDMA1; - __IO uint32_t I2SDMA2; - __IO uint32_t I2SIRQ; - __IO uint32_t I2STXRATE; - __IO uint32_t I2SRXRATE; - __IO uint32_t I2STXBITRATE; - __IO uint32_t I2SRXBITRATE; - __IO uint32_t I2STXMODE; - __IO uint32_t I2SRXMODE; -} LPC_I2S_TypeDef; - -/*------------- Real-Time Clock (RTC) ----------------------------------------*/ -typedef struct -{ - __IO uint8_t ILR; - uint8_t RESERVED0[3]; - __IO uint8_t CTC; - uint8_t RESERVED1[3]; - __IO uint8_t CCR; - uint8_t RESERVED2[3]; - __IO uint8_t CIIR; - uint8_t RESERVED3[3]; - __IO uint8_t AMR; - uint8_t RESERVED4[3]; - __I uint32_t CTIME0; - __I uint32_t CTIME1; - __I uint32_t CTIME2; - __IO uint8_t SEC; - uint8_t RESERVED5[3]; - __IO uint8_t MIN; - uint8_t RESERVED6[3]; - __IO uint8_t HOUR; - uint8_t RESERVED7[3]; - __IO uint8_t DOM; - uint8_t RESERVED8[3]; - __IO uint8_t DOW; - uint8_t RESERVED9[3]; - __IO uint16_t DOY; - uint16_t RESERVED10; - __IO uint8_t MONTH; - uint8_t RESERVED11[3]; - __IO uint16_t YEAR; - uint16_t RESERVED12; - __IO uint32_t CALIBRATION; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; - __IO uint8_t WAKEUPDIS; - uint8_t RESERVED13[3]; - __IO uint8_t PWRCTRL; - uint8_t RESERVED14[3]; - __IO uint8_t ALSEC; - uint8_t RESERVED15[3]; - __IO uint8_t ALMIN; - uint8_t RESERVED16[3]; - __IO uint8_t ALHOUR; - uint8_t RESERVED17[3]; - __IO uint8_t ALDOM; - uint8_t RESERVED18[3]; - __IO uint8_t ALDOW; - uint8_t RESERVED19[3]; - __IO uint16_t ALDOY; - uint16_t RESERVED20; - __IO uint8_t ALMON; - uint8_t RESERVED21[3]; - __IO uint16_t ALYEAR; - uint16_t RESERVED22; -} LPC_RTC_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint8_t WDMOD; - uint8_t RESERVED0[3]; - __IO uint32_t WDTC; - __O uint8_t WDFEED; - uint8_t RESERVED1[3]; - __I uint32_t WDTV; - __IO uint32_t WDCLKSEL; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t ADCR; - __IO uint32_t ADGDR; - uint32_t RESERVED0; - __IO uint32_t ADINTEN; - __I uint32_t ADDR0; - __I uint32_t ADDR1; - __I uint32_t ADDR2; - __I uint32_t ADDR3; - __I uint32_t ADDR4; - __I uint32_t ADDR5; - __I uint32_t ADDR6; - __I uint32_t ADDR7; - __I uint32_t ADSTAT; - __IO uint32_t ADTRM; -} LPC_ADC_TypeDef; - -/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ -typedef struct -{ - __IO uint32_t DACR; - __IO uint32_t DACCTRL; - __IO uint16_t DACCNTVAL; -} LPC_DAC_TypeDef; - -/*------------- Multimedia Card Interface (MCI) ------------------------------*/ -typedef struct -{ - __IO uint32_t MCIPower; /* Power control */ - __IO uint32_t MCIClock; /* Clock control */ - __IO uint32_t MCIArgument; - __IO uint32_t MMCCommand; - __I uint32_t MCIRespCmd; - __I uint32_t MCIResponse0; - __I uint32_t MCIResponse1; - __I uint32_t MCIResponse2; - __I uint32_t MCIResponse3; - __IO uint32_t MCIDataTimer; - __IO uint32_t MCIDataLength; - __IO uint32_t MCIDataCtrl; - __I uint32_t MCIDataCnt; -} LPC_MCI_TypeDef; - -/*------------- Controller Area Network (CAN) --------------------------------*/ -typedef struct -{ - __IO uint32_t mask[512]; /* ID Masks */ -} LPC_CANAF_RAM_TypeDef; - -typedef struct /* Acceptance Filter Registers */ -{ - __IO uint32_t AFMR; - __IO uint32_t SFF_sa; - __IO uint32_t SFF_GRP_sa; - __IO uint32_t EFF_sa; - __IO uint32_t EFF_GRP_sa; - __IO uint32_t ENDofTable; - __I uint32_t LUTerrAd; - __I uint32_t LUTerr; -} LPC_CANAF_TypeDef; - -typedef struct /* Central Registers */ -{ - __I uint32_t CANTxSR; - __I uint32_t CANRxSR; - __I uint32_t CANMSR; -} LPC_CANCR_TypeDef; - -typedef struct /* Controller Registers */ -{ - __IO uint32_t MOD; - __O uint32_t CMR; - __IO uint32_t GSR; - __I uint32_t ICR; - __IO uint32_t IER; - __IO uint32_t BTR; - __IO uint32_t EWL; - __I uint32_t SR; - __IO uint32_t RFS; - __IO uint32_t RID; - __IO uint32_t RDA; - __IO uint32_t RDB; - __IO uint32_t TFI1; - __IO uint32_t TID1; - __IO uint32_t TDA1; - __IO uint32_t TDB1; - __IO uint32_t TFI2; - __IO uint32_t TID2; - __IO uint32_t TDA2; - __IO uint32_t TDB2; - __IO uint32_t TFI3; - __IO uint32_t TID3; - __IO uint32_t TDA3; - __IO uint32_t TDB3; -} LPC_CAN_TypeDef; - -/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ -typedef struct /* Common Registers */ -{ - __I uint32_t DMACIntStat; - __I uint32_t DMACIntTCStat; - __O uint32_t DMACIntTCClear; - __I uint32_t DMACIntErrStat; - __O uint32_t DMACIntErrClr; - __I uint32_t DMACRawIntTCStat; - __I uint32_t DMACRawIntErrStat; - __I uint32_t DMACEnbldChns; - __IO uint32_t DMACSoftBReq; - __IO uint32_t DMACSoftSReq; - __IO uint32_t DMACSoftLBReq; - __IO uint32_t DMACSoftLSReq; - __IO uint32_t DMACConfig; - __IO uint32_t DMACSync; -} LPC_GPDMA_TypeDef; - -typedef struct /* Channel Registers */ -{ - __IO uint32_t DMACCSrcAddr; - __IO uint32_t DMACCDestAddr; - __IO uint32_t DMACCLLI; - __IO uint32_t DMACCControl; - __IO uint32_t DMACCConfig; -} LPC_GPDMACH_TypeDef; - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t HcRevision; /* USB Host Registers */ - __IO uint32_t HcControl; - __IO uint32_t HcCommandStatus; - __IO uint32_t HcInterruptStatus; - __IO uint32_t HcInterruptEnable; - __IO uint32_t HcInterruptDisable; - __IO uint32_t HcHCCA; - __I uint32_t HcPeriodCurrentED; - __IO uint32_t HcControlHeadED; - __IO uint32_t HcControlCurrentED; - __IO uint32_t HcBulkHeadED; - __IO uint32_t HcBulkCurrentED; - __I uint32_t HcDoneHead; - __IO uint32_t HcFmInterval; - __I uint32_t HcFmRemaining; - __I uint32_t HcFmNumber; - __IO uint32_t HcPeriodicStart; - __IO uint32_t HcLSTreshold; - __IO uint32_t HcRhDescriptorA; - __IO uint32_t HcRhDescriptorB; - __IO uint32_t HcRhStatus; - __IO uint32_t HcRhPortStatus1; - __IO uint32_t HcRhPortStatus2; - uint32_t RESERVED0[40]; - __I uint32_t Module_ID; - - __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ - __IO uint32_t OTGIntEn; - __O uint32_t OTGIntSet; - __O uint32_t OTGIntClr; - __IO uint32_t OTGStCtrl; - __IO uint32_t OTGTmr; - uint32_t RESERVED1[58]; - - __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t USBDevIntEn; - __O uint32_t USBDevIntClr; - __O uint32_t USBDevIntSet; - - __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ - __I uint32_t USBCmdData; - - __I uint32_t USBRxData; /* USB Device Transfer Registers */ - __O uint32_t USBTxData; - __I uint32_t USBRxPLen; - __O uint32_t USBTxPLen; - __IO uint32_t USBCtrl; - __O uint32_t USBDevIntPri; - - __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ - __IO uint32_t USBEpIntEn; - __O uint32_t USBEpIntClr; - __O uint32_t USBEpIntSet; - __O uint32_t USBEpIntPri; - - __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ - __O uint32_t USBEpInd; - __IO uint32_t USBMaxPSize; - - __I uint32_t USBDMARSt; /* USB Device DMA Registers */ - __O uint32_t USBDMARClr; - __O uint32_t USBDMARSet; - uint32_t RESERVED2[9]; - __IO uint32_t USBUDCAH; - __I uint32_t USBEpDMASt; - __O uint32_t USBEpDMAEn; - __O uint32_t USBEpDMADis; - __I uint32_t USBDMAIntSt; - __IO uint32_t USBDMAIntEn; - uint32_t RESERVED3[2]; - __I uint32_t USBEoTIntSt; - __O uint32_t USBEoTIntClr; - __O uint32_t USBEoTIntSet; - __I uint32_t USBNDDRIntSt; - __O uint32_t USBNDDRIntClr; - __O uint32_t USBNDDRIntSet; - __I uint32_t USBSysErrIntSt; - __O uint32_t USBSysErrIntClr; - __O uint32_t USBSysErrIntSet; - uint32_t RESERVED4[15]; - - __I uint32_t I2C_RX; /* USB OTG I2C Registers */ - __O uint32_t I2C_WO; - __I uint32_t I2C_STS; - __IO uint32_t I2C_CTL; - __IO uint32_t I2C_CLKHI; - __O uint32_t I2C_CLKLO; - uint32_t RESERVED5[823]; - - union { - __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ - __IO uint32_t OTGClkCtrl; - }; - union { - __I uint32_t USBClkSt; - __I uint32_t OTGClkSt; - }; -} LPC_USB_TypeDef; - -/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ -typedef struct -{ - __IO uint32_t MAC1; /* MAC Registers */ - __IO uint32_t MAC2; - __IO uint32_t IPGT; - __IO uint32_t IPGR; - __IO uint32_t CLRT; - __IO uint32_t MAXF; - __IO uint32_t SUPP; - __IO uint32_t TEST; - __IO uint32_t MCFG; - __IO uint32_t MCMD; - __IO uint32_t MADR; - __O uint32_t MWTD; - __I uint32_t MRDD; - __I uint32_t MIND; - uint32_t RESERVED0[2]; - __IO uint32_t SA0; - __IO uint32_t SA1; - __IO uint32_t SA2; - uint32_t RESERVED1[45]; - __IO uint32_t Command; /* Control Registers */ - __I uint32_t Status; - __IO uint32_t RxDescriptor; - __IO uint32_t RxStatus; - __IO uint32_t RxDescriptorNumber; - __I uint32_t RxProduceIndex; - __IO uint32_t RxConsumeIndex; - __IO uint32_t TxDescriptor; - __IO uint32_t TxStatus; - __IO uint32_t TxDescriptorNumber; - __IO uint32_t TxProduceIndex; - __I uint32_t TxConsumeIndex; - uint32_t RESERVED2[10]; - __I uint32_t TSV0; - __I uint32_t TSV1; - __I uint32_t RSV; - uint32_t RESERVED3[3]; - __IO uint32_t FlowControlCounter; - __I uint32_t FlowControlStatus; - uint32_t RESERVED4[34]; - __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ - __IO uint32_t RxFilterWoLStatus; - __IO uint32_t RxFilterWoLClear; - uint32_t RESERVED5; - __IO uint32_t HashFilterL; - __IO uint32_t HashFilterH; - uint32_t RESERVED6[882]; - __I uint32_t IntStatus; /* Module Control Registers */ - __IO uint32_t IntEnable; - __O uint32_t IntClear; - __O uint32_t IntSet; - uint32_t RESERVED7; - __IO uint32_t PowerDown; - uint32_t RESERVED8; - __IO uint32_t Module_ID; -} LPC_EMAC_TypeDef; - -#if defined ( __CC_ARM ) - #pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ - -/* AHB Peripheral # 0 */ - -/* -#define FLASH_BASE (0x00000000UL) -#define RAM_BASE (0x10000000UL) -#define GPIO_BASE (0x2009C000UL) -#define APB0_BASE (0x40000000UL) -#define APB1_BASE (0x40080000UL) -#define AHB_BASE (0x50000000UL) -#define CM3_BASE (0xE0000000UL) -*/ - -// TODO - #define VIC_BASE_ADDR 0xFFFFF000 - -#define LPC_WDT_BASE (0xE0000000) -#define LPC_TIM0_BASE (0xE0004000) -#define LPC_TIM1_BASE (0xE0008000) -#define LPC_UART0_BASE (0xE000C000) -#define LPC_UART1_BASE (0xE0010000) -#define LPC_PWM1_BASE (0xE0018000) -#define LPC_I2C0_BASE (0xE001C000) -#define LPC_SPI_BASE (0xE0020000) -#define LPC_RTC_BASE (0xE0024000) -#define LPC_GPIOINT_BASE (0xE0028080) -#define LPC_PINCON_BASE (0xE002C000) -#define LPC_SSP1_BASE (0xE0030000) -#define LPC_ADC_BASE (0xE0034000) -#define LPC_CANAF_RAM_BASE (0xE0038000) -#define LPC_CANAF_BASE (0xE003C000) -#define LPC_CANCR_BASE (0xE0040000) -#define LPC_CAN1_BASE (0xE0044000) -#define LPC_CAN2_BASE (0xE0048000) -#define LPC_I2C1_BASE (0xE005C000) -#define LPC_SSP0_BASE (0xE0068000) -#define LPC_DAC_BASE (0xE006C000) -#define LPC_TIM2_BASE (0xE0070000) -#define LPC_TIM3_BASE (0xE0074000) -#define LPC_UART2_BASE (0xE0078000) -#define LPC_UART3_BASE (0xE007C000) -#define LPC_I2C2_BASE (0xE0080000) -#define LPC_I2S_BASE (0xE0088000) -#define LPC_MCI_BASE (0xE008C000) -#define LPC_SC_BASE (0xE01FC000) -#define LPC_EMAC_BASE (0xFFE00000) -#define LPC_GPDMA_BASE (0xFFE04000) -#define LPC_GPDMACH0_BASE (0xFFE04100) -#define LPC_GPDMACH1_BASE (0xFFE04120) -#define LPC_USB_BASE (0xFFE0C000) -#define LPC_VIC_BASE (0xFFFFF000) - -/* GPIOs */ -#define LPC_GPIO0_BASE (0x3FFFC000) -#define LPC_GPIO1_BASE (0x3FFFC020) -#define LPC_GPIO2_BASE (0x3FFFC040) -#define LPC_GPIO3_BASE (0x3FFFC060) -#define LPC_GPIO4_BASE (0x3FFFC080) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE) -#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE) -#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE) -#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE) -#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE) -#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE) -#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE) -#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE) -#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE) -#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE) -#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE) -#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE) -#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE) -#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE) -#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE) -#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE) -#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE) -#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE) -#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE) -#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE) -#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE) -#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE) -#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE) -#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE) -#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE) -#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE) -#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE) -#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE) -#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) -#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE) -#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE) -#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE) -#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE) -#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE) -#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE) -#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE) -#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE) -#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE) -#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE) -#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE) - -#ifdef __cplusplus - } -#endif - -#endif // __LPC23xx_H - diff --git a/targetlibs/libmbed/LPC2368/PeripheralNames.h b/targetlibs/libmbed/LPC2368/PeripheralNames.h deleted file mode 100644 index bda583dca..000000000 --- a/targetlibs/libmbed/LPC2368/PeripheralNames.h +++ /dev/null @@ -1,80 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - UART_0 = (int)LPC_UART0_BASE, - UART_1 = (int)LPC_UART1_BASE, - UART_2 = (int)LPC_UART2_BASE, - UART_3 = (int)LPC_UART3_BASE -} UARTName; - -typedef enum { - ADC0_0 = 0, - ADC0_1, - ADC0_2, - ADC0_3, - ADC0_4, - ADC0_5, - ADC0_6, - ADC0_7 -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - -typedef enum { - SPI_0 = (int)LPC_SSP0_BASE, - SPI_1 = (int)LPC_SSP1_BASE -} SPIName; - -typedef enum { - I2C_0 = (int)LPC_I2C0_BASE, - I2C_1 = (int)LPC_I2C1_BASE, - I2C_2 = (int)LPC_I2C2_BASE -} I2CName; - -typedef enum { - PWM_1 = 1, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6 -} PWMName; - -typedef enum { - CAN_1 = (int)LPC_CAN1_BASE, - CAN_2 = (int)LPC_CAN2_BASE -} CANName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/PinNames.h b/targetlibs/libmbed/LPC2368/PinNames.h deleted file mode 100644 index 69ab91fe5..000000000 --- a/targetlibs/libmbed/LPC2368/PinNames.h +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 5 - -typedef enum { - // LPC Pin Names - P0_0 = LPC_GPIO0_BASE, - P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31, - P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31, - P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31, - P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31, - P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31, - - // mbed DIP Pin Names - p5 = P0_9, - p6 = P0_8, - p7 = P0_7, - p8 = P0_6, - p9 = P0_0, - p10 = P0_1, - p11 = P0_18, - p12 = P0_17, - p13 = P0_15, - p14 = P0_16, - p15 = P0_23, - p16 = P0_24, - p17 = P0_25, - p18 = P0_26, - p19 = P1_30, - p20 = P1_31, - p21 = P2_5, - p22 = P2_4, - p23 = P2_3, - p24 = P2_2, - p25 = P2_1, - p26 = P2_0, - p27 = P0_11, - p28 = P0_10, - p29 = P0_5, - p30 = P0_4, - - // Other mbed Pin Names - LED1 = P1_18, - LED2 = P1_20, - LED3 = P1_21, - LED4 = P1_23, - - USBTX = P0_2, - USBRX = P0_3, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullUp = 0, - PullDown = 3, - PullNone = 2, - OpenDrain = 4 -} PinMode; - -// version of PINCON_TypeDef using register arrays -typedef struct { - __IO uint32_t PINSEL[11]; - uint32_t RESERVED0[5]; - __IO uint32_t PINMODE[10]; -} PINCONARRAY_TypeDef; - -#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/PortNames.h b/targetlibs/libmbed/LPC2368/PortNames.h deleted file mode 100644 index 270cdeecb..000000000 --- a/targetlibs/libmbed/LPC2368/PortNames.h +++ /dev/null @@ -1,34 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, - Port1 = 1, - Port2 = 2, - Port3 = 3, - Port4 = 4 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targetlibs/libmbed/LPC2368/cmsis.h b/targetlibs/libmbed/LPC2368/cmsis.h deleted file mode 100644 index 3926baf40..000000000 --- a/targetlibs/libmbed/LPC2368/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC2368 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC23xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targetlibs/libmbed/LPC2368/cmsis_nvic.h b/targetlibs/libmbed/LPC2368/cmsis_nvic.h deleted file mode 100644 index 299d3879b..000000000 --- a/targetlibs/libmbed/LPC2368/cmsis_nvic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/core_arm7.h b/targetlibs/libmbed/LPC2368/core_arm7.h deleted file mode 100644 index d64d739c3..000000000 --- a/targetlibs/libmbed/LPC2368/core_arm7.h +++ /dev/null @@ -1,265 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (C) 2008-2009 ARM Limited. All rights reserved. - * - * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! - * based on core_cm3.h, V1.20 - */ - -#ifndef __ARM7_CORE_H__ -#define __ARM7_CORE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -/** - * Lint configuration \n - * ----------------------- \n - * - * The following Lint messages will be suppressed and not shown: \n - * \n - * --- Error 10: --- \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' \n - * \n - * --- Error 530: --- \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n - * \n - * --- Error 550: --- \n - * __regBasePri = (basePri & 0x1ff); \n - * } \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n - * \n - * --- Error 754: --- \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n - * \n - * --- Error 750: --- \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n - * \n - * --- Error 528: --- \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n - * \n - * --- Error 751: --- \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n - * \n - * \n - * Note: To re-enable a Message, insert a space before 'lint' * \n - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - -#include /* Include standard types */ - -#if defined ( __CC_ARM ) -/** - * @brief Return the Main Stack Pointer (current ARM7 stack) - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); -#endif - - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - -typedef struct -{ - uint32_t IRQStatus; - uint32_t FIQStatus; - uint32_t RawIntr; - uint32_t IntSelect; - uint32_t IntEnable; - uint32_t IntEnClr; - uint32_t SoftInt; - uint32_t SoftIntClr; - uint32_t Protection; - uint32_t SWPriorityMask; - uint32_t RESERVED0[54]; - uint32_t VectAddr[32]; - uint32_t RESERVED1[32]; - uint32_t VectPriority[32]; - uint32_t RESERVED2[800]; - uint32_t Address; -} NVIC_TypeDef; - -#define NVIC_BASE (0xFFFFF000) -#define NVIC (( NVIC_TypeDef *) NVIC_BASE) - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus -#define __I volatile /*!< defines 'read only' permissions */ -#else -#define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -//#define __WFI __wfi -//#define __WFE __wfe -//#define __SEV __sev -//#define __ISB() __isb(0) -//#define __DSB() __dsb(0) -//#define __DMB() __dmb(0) -//#define __REV __rev -//#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - -#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \ - LPC_VIC->IntEnClr = 0xffffffff - -#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ -#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - -static __INLINE void __enable_irq() { - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - -static __INLINE void __disable_irq() { - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - // return (old & 0x80) == 0; -} - -static __INLINE void __NOP() { __ASM volatile ("nop"); } - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn_Type IRQn specifies the interrupt number - * @return none - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->IntEnable = 1 << (uint32_t)IRQn; -} - - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn_Type IRQn is the positive number of the external interrupt - * @return none - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->IntEnClr = 1 << (uint32_t)IRQn; -} - - -#ifdef __cplusplus -} -#endif - -#endif /* __ARM7_CORE_H__ */ - -/*lint -restore */ diff --git a/targetlibs/libmbed/LPC2368/device.h b/targetlibs/libmbed/LPC2368/device.h deleted file mode 100644 index 9a20ae4a3..000000000 --- a/targetlibs/libmbed/LPC2368/device.h +++ /dev/null @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 1 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 1 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/targetlibs/libmbed/LPC2368/gpio_object.h b/targetlibs/libmbed/LPC2368/gpio_object.h deleted file mode 100644 index 8f8d5eb59..000000000 --- a/targetlibs/libmbed/LPC2368/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/objects.h b/targetlibs/libmbed/LPC2368/objects.h deleted file mode 100644 index 41d717adc..000000000 --- a/targetlibs/libmbed/LPC2368/objects.h +++ /dev/null @@ -1,78 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t port; - uint32_t pin; - uint32_t ch; -}; - -struct port_s { - __IO uint32_t *reg_dir; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - __IO uint32_t *MR; - PWMName pwm; -}; - -struct serial_s { - LPC_UART_TypeDef *uart; - int index; -}; - -struct analogin_s { - ADCName adc; -}; - -struct dac_s { - DACName dac; -}; - -struct can_s { - LPC_CAN_TypeDef *dev; -}; - -struct i2c_s { - LPC_I2C_TypeDef *i2c; -}; - -struct spi_s { - LPC_SSP_TypeDef *spi; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/system_LPC23xx.h b/targetlibs/libmbed/LPC2368/system_LPC23xx.h deleted file mode 100644 index 48a071885..000000000 --- a/targetlibs/libmbed/LPC2368/system_LPC23xx.h +++ /dev/null @@ -1,44 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (C) 2008-2009 ARM Limited. All rights reserved. - * - * ARM7 version of CMSIS-like functionality - not advised for use outside mbed! - * based on cmsis system_LPC17xx.h - */ - -#ifndef __SYSTEM_LPC23xx_H -#define __SYSTEM_LPC23xx_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC2368/vector_defns.h b/targetlibs/libmbed/LPC2368/vector_defns.h deleted file mode 100644 index cb563d4e5..000000000 --- a/targetlibs/libmbed/LPC2368/vector_defns.h +++ /dev/null @@ -1,75 +0,0 @@ -/* mbed Microcontroller Library - Vectors - * Copyright (c) 2006-2009 ARM Limited. All rights reserved. - */ - -#ifndef MBED_VECTOR_DEFNS_H -#define MBED_VECTOR_DEFNS_H - -// Assember Macros -#ifdef __ARMCC_VERSION -#define EXPORT(x) EXPORT x -#define WEAK_EXPORT(x) EXPORT x [WEAK] -#define IMPORT(x) IMPORT x -#define LABEL(x) x -#else -#define EXPORT(x) .global x -#define WEAK_EXPORT(x) .weak x -#define IMPORT(x) .global x -#define LABEL(x) x: -#endif - -// RealMonitor -// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker - -// RealMonitor entry points -#define rm_init_entry 0x7fffff91 -#define rm_undef_handler 0x7fffffa0 -#define rm_prefetchabort_handler 0x7fffffb0 -#define rm_dataabort_handler 0x7fffffc0 -#define rm_irqhandler2 0x7fffffe0 -//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 -#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 - -// Unofficial RealMonitor entry points and variables -#define RM_MSG_SWI 0x00940000 -#define StateP 0x40000040 - -// VIC register addresses -#define VIC_Base 0xfffff000 -#define VICAddress_Offset 0xf00 -#define VICVectAddr2_Offset 0x108 -#define VICVectAddr3_Offset 0x10c -#define VICIntEnClr_Offset 0x014 -#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) -#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) -#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) - -// ARM Mode bits and Interrupt flags in PSRs -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F -#define I_Bit 0x80 // when I bit is set, IRQ is disabled -#define F_Bit 0x40 // when F bit is set, FIQ is disabled - -// MCU RAM -#define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base -#define LPC2368_RAM_SIZE 0x8000 // 32KB - -// ISR Stack Allocation -#define UND_stack_size 0x00000040 -#define SVC_stack_size 0x00000040 -#define ABT_stack_size 0x00000040 -#define FIQ_stack_size 0x00000000 -#define IRQ_stack_size 0x00000040 - -#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) - -// Full Descending Stack, so top-most stack points to just above the top of RAM -#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE) -#define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size) - -#endif diff --git a/targetlibs/libmbed/LPC812/LPC8xx.h b/targetlibs/libmbed/LPC812/LPC8xx.h deleted file mode 100644 index 9160321a7..000000000 --- a/targetlibs/libmbed/LPC812/LPC8xx.h +++ /dev/null @@ -1,687 +0,0 @@ -/**************************************************************************** - * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ - * Project: NXP LPC8xx software example - * - * Description: - * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for - * NXP LPC800 Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' - * relevant copyright in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. -****************************************************************************/ -#ifndef __LPC8xx_H__ -#define __LPC8xx_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup LPC8xx_Definitions LPC8xx Definitions - This file defines all structures and symbols for LPC8xx: - - Registers and bitfields - - peripheral base address - - PIO definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions - Configuration of the Cortex-M0+ Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** LPC8xx Specific Interrupt Numbers ********************************************************/ - SPI0_IRQn = 0, /*!< SPI0 */ - SPI1_IRQn = 1, /*!< SPI1 */ - Reserved0_IRQn = 2, /*!< Reserved Interrupt */ - UART0_IRQn = 3, /*!< USART0 */ - UART1_IRQn = 4, /*!< USART1 */ - UART2_IRQn = 5, /*!< USART2 */ - Reserved1_IRQn = 6, /*!< Reserved Interrupt */ - Reserved2_IRQn = 7, /*!< Reserved Interrupt */ - I2C_IRQn = 8, /*!< I2C */ - SCT_IRQn = 9, /*!< SCT */ - MRT_IRQn = 10, /*!< MRT */ - CMP_IRQn = 11, /*!< CMP */ - WDT_IRQn = 12, /*!< WDT */ - BOD_IRQn = 13, /*!< BOD */ - Reserved3_IRQn = 14, /*!< Reserved Interrupt */ - WKT_IRQn = 15, /*!< WKT Interrupt */ - Reserved4_IRQn = 16, /*!< Reserved Interrupt */ - Reserved5_IRQn = 17, /*!< Reserved Interrupt */ - Reserved6_IRQn = 18, /*!< Reserved Interrupt */ - Reserved7_IRQn = 19, /*!< Reserved Interrupt */ - Reserved8_IRQn = 20, /*!< Reserved Interrupt */ - Reserved9_IRQn = 21, /*!< Reserved Interrupt */ - Reserved10_IRQn = 22, /*!< Reserved Interrupt */ - Reserved11_IRQn = 23, /*!< Reserved Interrupt */ - PININT0_IRQn = 24, /*!< External Interrupt 0 */ - PININT1_IRQn = 25, /*!< External Interrupt 1 */ - PININT2_IRQn = 26, /*!< External Interrupt 2 */ - PININT3_IRQn = 27, /*!< External Interrupt 3 */ - PININT4_IRQn = 28, /*!< External Interrupt 4 */ - PININT5_IRQn = 29, /*!< External Interrupt 5 */ - PININT6_IRQn = 30, /*!< External Interrupt 6 */ - PININT7_IRQn = 31, /*!< External Interrupt 7 */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*@}*/ /* end of group LPC8xx_CMSIS */ - - -#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -#include "system_LPC8xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block - @{ -*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ - uint32_t RESERVED0[4]; - - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ - uint32_t RESERVED6[18]; - - __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED7; - __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ - __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - uint32_t RESERVED9[12]; - __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ - uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - uint32_t RESERVED11[27]; - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ -} LPC_SYSCON_TypeDef; -/*@}*/ /* end of group LPC8xx_SYSCON */ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ - __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ - __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ - __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ - __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ - __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ - __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ - __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ - __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ - __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ - __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ - __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ -} LPC_IOCON_TypeDef; -/*@}*/ /* end of group LPC8xx_IOCON */ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) - */ -typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ - __I uint32_t RESERVED2; - __I uint32_t FMSW0; -} LPC_FLASHCTRL_TypeDef; -/*@}*/ /* end of group LPC8xx_FLASHCTRL */ - - -/*------------- Power Management Unit (PMU) --------------------------*/ -/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit - @{ -*/ -typedef struct -{ - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ - __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ - __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ - __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ - __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ -} LPC_PMU_TypeDef; -/*@}*/ /* end of group LPC8xx_PMU */ - - -/*------------- Switch Matrix Port --------------------------*/ -/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port - @{ -*/ -typedef struct -{ - union { - __IO uint32_t PINASSIGN[9]; - struct { - __IO uint32_t PINASSIGN0; - __IO uint32_t PINASSIGN1; - __IO uint32_t PINASSIGN2; - __IO uint32_t PINASSIGN3; - __IO uint32_t PINASSIGN4; - __IO uint32_t PINASSIGN5; - __IO uint32_t PINASSIGN6; - __IO uint32_t PINASSIGN7; - __IO uint32_t PINASSIGN8; - }; - }; - __I uint32_t RESERVED0[103]; - __IO uint32_t PINENABLE0; -} LPC_SWM_TypeDef; -/*@}*/ /* end of group LPC8xx_SWM */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ - __I uint16_t RESERVED0[2039]; - __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ - uint32_t RESERVED1[1006]; - __IO uint32_t DIR0; /* 0x2000 */ - uint32_t RESERVED2[31]; - __IO uint32_t MASK0; /* 0x2080 */ - uint32_t RESERVED3[31]; - __IO uint32_t PIN0; /* 0x2100 */ - uint32_t RESERVED4[31]; - __IO uint32_t MPIN0; /* 0x2180 */ - uint32_t RESERVED5[31]; - __IO uint32_t SET0; /* 0x2200 */ - uint32_t RESERVED6[31]; - __O uint32_t CLR0; /* 0x2280 */ - uint32_t RESERVED7[31]; - __O uint32_t NOT0; /* 0x2300 */ - -} LPC_GPIO_PORT_TypeDef; - - -// ------------------------------------------------------------------------------------------------ -// ----- PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) - */ - -typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ - __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ - __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ -} LPC_PIN_INT_TypeDef; - - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -/** @addtogroup LPC8xx_CRC - @{ -*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - __O uint32_t WR_DATA_DWORD; - __O uint16_t WR_DATA_WORD; - uint16_t RESERVED_WORD; - __O uint8_t WR_DATA_BYTE; - uint8_t RESERVED_BYTE[3]; - }; -} LPC_CRC_TypeDef; -/*@}*/ /* end of group LPC8xx_CRC */ - -/*------------- Comparator (CMP) --------------------------------------------------*/ -/** @addtogroup LPC8xx_CMP LPC8xx Comparator - @{ -*/ -typedef struct { /*!< (@ 0x40024000) CMP Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ - __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ -} LPC_CMP_TypeDef; -/*@}*/ /* end of group LPC8xx_CMP */ - - -/*------------- Wakeup Timer (WKT) --------------------------------------------------*/ -/** @addtogroup LPC8xx_WKT - @{ -*/ -typedef struct { /*!< (@ 0x40028000) WKT Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ - uint32_t Reserved[2]; - __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ -} LPC_WKT_TypeDef; -/*@}*/ /* end of group LPC8xx_WKT */ - - -/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ -typedef struct { -__IO uint32_t INTVAL; -__IO uint32_t TIMER; -__IO uint32_t CTRL; -__IO uint32_t STAT; -} MRT_Channel_cfg_Type; - -typedef struct { - MRT_Channel_cfg_Type Channel[4]; - uint32_t Reserved0[1]; - __IO uint32_t IDLE_CH; - __IO uint32_t IRQ_FLAG; -} LPC_MRT_TypeDef; - - -/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ -/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter - @{ -*/ -/** - * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) - */ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t CTRL; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDATA; - __I uint32_t RXDATA_STAT; - __IO uint32_t TXDATA; - __IO uint32_t BRG; /* 0x20 */ - __IO uint32_t INTSTAT; -} LPC_USART_TypeDef; - -/*@}*/ /* end of group LPC8xx_USART */ - - -/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ -/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t DLY; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDAT; - __IO uint32_t TXDATCTL; - __IO uint32_t TXDAT; - __IO uint32_t TXCTRL; /* 0x20 */ - __IO uint32_t DIV; - __I uint32_t INTSTAT; -} LPC_SPI_TypeDef; -/*@}*/ /* end of group LPC8xx_SPI */ - - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @addtogroup LPC8xx_I2C I2C-Bus Interface - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; - __IO uint32_t TIMEOUT; /* 0x10 */ - __IO uint32_t DIV; - __IO uint32_t INTSTAT; - uint32_t Reserved0[1]; - __IO uint32_t MSTCTL; /* 0x20 */ - __IO uint32_t MSTTIME; - __IO uint32_t MSTDAT; - uint32_t Reserved1[5]; - __IO uint32_t SLVCTL; /* 0x40 */ - __IO uint32_t SLVDAT; - __IO uint32_t SLVADR0; - __IO uint32_t SLVADR1; - __IO uint32_t SLVADR2; /* 0x50 */ - __IO uint32_t SLVADR3; - __IO uint32_t SLVQUAL0; - uint32_t Reserved2[9]; - __I uint32_t MONRXDAT; /* 0x80 */ -} LPC_I2C_TypeDef; - -/*@}*/ /* end of group LPC8xx_I2C */ - -/** - * @brief State Configurable Timer (SCT) (SCT) - */ - -/** - * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) - */ - -#define CONFIG_SCT_nEV (6) /* Number of events */ -#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ -#define CONFIG_SCT_nOU (4) /* Number of outputs */ - -typedef struct -{ - __IO uint32_t CONFIG; /* 0x000 Configuration Register */ - union { - __IO uint32_t CTRL_U; /* 0x004 Control Register */ - struct { - __IO uint16_t CTRL_L; /* 0x004 low control register */ - __IO uint16_t CTRL_H; /* 0x006 high control register */ - }; - }; - __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ - __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ - __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ - __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ - __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ - __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ - __IO uint16_t START_L; /* 0x014 start register for counter L */ - __IO uint16_t START_H; /* 0x016 start register for counter H */ - uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ - union { - __IO uint32_t COUNT_U; /* 0x040 counter register */ - struct { - __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ - __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ - }; - }; - __IO uint16_t STATE_L; /* 0x044 state register for counter L */ - __IO uint16_t STATE_H; /* 0x046 state register for counter H */ - __I uint32_t INPUT; /* 0x048 input register */ - __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ - __IO uint32_t OUTPUT; /* 0x050 output register */ - __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ - __IO uint32_t RES; /* 0x058 conflict resolution register */ - uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ - __IO uint32_t EVEN; /* 0x0F0 event enable register */ - __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ - __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ - __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ - - union { - __IO union { /* 0x100-... Match / Capture value */ - uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCH[i].L Access to L value */ - uint16_t H; /* SCTMATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - __I union { - uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAP[i].L Access to H value */ - uint16_t H; /* SCTCAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - - uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ - - union { - __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ - __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ - }; - uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ - union { - __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ - __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ - }; - - uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ - - - union { - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ - - union { - __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ - __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ - }; - uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ - union { - __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ - __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ - }; - uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ - - __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /* Output n Set Register */ - uint32_t CLR; /* Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ - - __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ - -} LPC_SCT_TypeDef; -/*@}*/ /* end of group LPC8xx_SCT */ - - -/*------------- Watchdog Timer (WWDT) -----------------------------------------*/ -/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer - @{ -*/ -typedef struct -{ - __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ - __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ - __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ - uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ - __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ - __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ -} LPC_WWDT_TypeDef; -/*@}*/ /* end of group LPC8xx_WDT */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_ROM_BASE (0x1FFF0000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) - -#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) -#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) -#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) -#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) -#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) -#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) - -/* AHB peripherals */ -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) - -#define LPC_GPIO_PORT_BASE (0xA0000000) -#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) -#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) - - -#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) -#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) - -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) -#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) -#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) -#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) -#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) - -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) - -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) -#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC8xx_H__ */ diff --git a/targetlibs/libmbed/LPC812/PeripheralNames.h b/targetlibs/libmbed/LPC812/PeripheralNames.h deleted file mode 100644 index 988c1cb89..000000000 --- a/targetlibs/libmbed/LPC812/PeripheralNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC812/PinNames.h b/targetlibs/libmbed/LPC812/PinNames.h deleted file mode 100644 index da918741b..000000000 --- a/targetlibs/libmbed/LPC812/PinNames.h +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - - D0 = P0_0, - D1 = P0_4, - D2 = P0_6, - D3 = P0_8, - D4 = P0_9, - - D7 = P0_7, - D8 = P0_17, - D9 = P0_16, - D10 = P0_13, - D11 = P0_14, - D12 = P0_15, - D13 = P0_12, - - A4 = P0_10, - A5 = P0_11, - - // LPC800-MAX board - LED_RED = P0_7, - LED_GREEN = P0_17, - LED_BLUE = P0_16, - - // mbed original LED naming - LED1 = LED_BLUE, - LED2 = LED_GREEN, - LED3 = LED_RED, - LED4 = LED_RED, - - // Serial to USB pins - USBTX = P0_6, - USBRX = P0_1, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4 -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC812/PortNames.h b/targetlibs/libmbed/LPC812/PortNames.h deleted file mode 100644 index bbd5b3110..000000000 --- a/targetlibs/libmbed/LPC812/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targetlibs/libmbed/LPC812/cmsis.h b/targetlibs/libmbed/LPC812/cmsis.h deleted file mode 100644 index 12302cc3a..000000000 --- a/targetlibs/libmbed/LPC812/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC8xx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC8xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targetlibs/libmbed/LPC812/cmsis_nvic.h b/targetlibs/libmbed/LPC812/cmsis_nvic.h deleted file mode 100644 index 299d3879b..000000000 --- a/targetlibs/libmbed/LPC812/cmsis_nvic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* mbed Microcontroller Library - cmsis_nvic - * Copyright (c) 2009-2011 ARM Limited. All rights reserved. - * - * CMSIS-style functionality to support dynamic vectors - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC812/core_cm0plus.h b/targetlibs/libmbed/LPC812/core_cm0plus.h deleted file mode 100644 index 469babd4c..000000000 --- a/targetlibs/libmbed/LPC812/core_cm0plus.h +++ /dev/null @@ -1,778 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.02 - * @date 05. November 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/targetlibs/libmbed/LPC812/core_cmFunc.h b/targetlibs/libmbed/LPC812/core_cmFunc.h deleted file mode 100644 index e42ceb161..000000000 --- a/targetlibs/libmbed/LPC812/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.02 - * @date 24. May 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/targetlibs/libmbed/LPC812/core_cmInstr.h b/targetlibs/libmbed/LPC812/core_cmInstr.h deleted file mode 100644 index 33a84312d..000000000 --- a/targetlibs/libmbed/LPC812/core_cmInstr.h +++ /dev/null @@ -1,643 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.03 - * @date 29. August 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/targetlibs/libmbed/LPC812/device.h b/targetlibs/libmbed/LPC812/device.h deleted file mode 100644 index ddb923bb8..000000000 --- a/targetlibs/libmbed/LPC812/device.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 0 -#define DEVICE_PORTOUT 0 -#define DEVICE_PORTINOUT 0 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 0 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 0 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif diff --git a/targetlibs/libmbed/LPC812/gpio_object.h b/targetlibs/libmbed/LPC812/gpio_object.h deleted file mode 100644 index 8f8d5eb59..000000000 --- a/targetlibs/libmbed/LPC812/gpio_object.h +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC812/objects.h b/targetlibs/libmbed/LPC812/objects.h deleted file mode 100644 index fdff3f71f..000000000 --- a/targetlibs/libmbed/LPC812/objects.h +++ /dev/null @@ -1,52 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t ch; -}; - -struct serial_s { - LPC_USART_TypeDef *uart; - unsigned char index; -}; - -struct i2c_s { - LPC_I2C_TypeDef *i2c; -}; - -struct spi_s { - LPC_SPI_TypeDef *spi; - unsigned char spi_n; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/LPC812/system_LPC8xx.h b/targetlibs/libmbed/LPC812/system_LPC8xx.h deleted file mode 100644 index 54493ff59..000000000 --- a/targetlibs/libmbed/LPC812/system_LPC8xx.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.h - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC8xx_H -#define __SYSTEM_LPC8xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC8xx_H */ diff --git a/targetlibs/libmbed/LPC812/uARM/LPC812.sct b/targetlibs/libmbed/LPC812/uARM/LPC812.sct deleted file mode 100644 index 2e6bbeed8..000000000 --- a/targetlibs/libmbed/LPC812/uARM/LPC812.sct +++ /dev/null @@ -1,14 +0,0 @@ - -LR_IROM1 0x00000000 0x4000 { ; load region size_region (32k) - ER_IROM1 0x00000000 0x4000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 - ; 8KB - 0xC0 = 0xF40 - RW_IRAM1 0x100000C0 0xF40 { - .ANY (+RW +ZI) - } -} - diff --git a/targetlibs/libmbed/LPC812/uARM/mbed.ar b/targetlibs/libmbed/LPC812/uARM/mbed.ar deleted file mode 100644 index f970fa734..000000000 Binary files a/targetlibs/libmbed/LPC812/uARM/mbed.ar and /dev/null differ diff --git a/targetlibs/libmbed/LocalFileSystem.h b/targetlibs/libmbed/LocalFileSystem.h deleted file mode 100644 index 9eb61a4b9..000000000 --- a/targetlibs/libmbed/LocalFileSystem.h +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_LOCALFILESYSTEM_H -#define MBED_LOCALFILESYSTEM_H - -#include "platform.h" - -#if DEVICE_LOCALFILESYSTEM - -#include "FileSystemLike.h" - -namespace mbed { - -FILEHANDLE local_file_open(const char* name, int flags); - -class LocalFileHandle : public FileHandle { - -public: - LocalFileHandle(FILEHANDLE fh); - - virtual int close(); - - virtual ssize_t write(const void *buffer, size_t length); - - virtual ssize_t read(void *buffer, size_t length); - - virtual int isatty(); - - virtual off_t lseek(off_t position, int whence); - - virtual int fsync(); - - virtual off_t flen(); - -protected: - FILEHANDLE _fh; - int pos; -}; - -/** A filesystem for accessing the local mbed Microcontroller USB disk drive - * - * This allows programs to read and write files on the same disk drive that is used to program the - * mbed Microcontroller. Once created, the standard C file access functions are used to open, - * read and write files. - * - * Example: - * @code - * #include "mbed.h" - * - * LocalFileSystem local("local"); // Create the local filesystem under the name "local" - * - * int main() { - * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing - * fprintf(fp, "Hello World!"); - * fclose(fp); - * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system - * - * DIR *d = opendir("/local"); // Opens the root directory of the local file system - * struct dirent *p; - * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system - * printf("%s\n", p->d_name); // to stdout. - * } - * closedir(d); - * } - * @endcode - * - * @note - * If the microcontroller program makes an access to the local drive, it will be marked as "removed" - * on the Host computer. This means it is no longer accessible from the Host Computer. - * - * The drive will only re-appear when the microcontroller program exists. Note that if the program does - * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again! - */ -class LocalFileSystem : public FileSystemLike { - -public: - LocalFileSystem(const char* n) : FileSystemLike(n) { - - } - - virtual FileHandle *open(const char* name, int flags); - virtual int remove(const char *filename); - virtual DirHandle *opendir(const char *name); -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/PortIn.h b/targetlibs/libmbed/PortIn.h deleted file mode 100644 index 44686325c..000000000 --- a/targetlibs/libmbed/PortIn.h +++ /dev/null @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTIN_H -#define MBED_PORTIN_H - -#include "platform.h" - -#if DEVICE_PORTIN - -#include "port_api.h" - -namespace mbed { - -/** A multiple pin digital input - * - * Example: - * @code - * // Switch on an LED if any of mbed pins 21-26 is high - * - * #include "mbed.h" - * - * PortIn p(Port2, 0x0000003F); // p21-p26 - * DigitalOut ind(LED4); - * - * int main() { - * while(1) { - * int pins = p.read(); - * if(pins) { - * ind = 1; - * } else { - * ind = 0; - * } - * } - * } - * @endcode - */ -class PortIn { -public: - - /** Create an PortIn, connected to the specified port - * - * @param port Port to connect to (Port0-Port5) - * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) - */ - PortIn(PortName port, int mask = 0xFFFFFFFF) { - port_init(&_port, port, mask, PIN_INPUT); - } - - /** Read the value currently output on the port - * - * @returns - * An integer with each bit corresponding to associated port pin setting - */ - int read() { - return port_read(&_port); - } - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone, OpenDrain - */ - void mode(PinMode mode) { - port_mode(&_port, mode); - } - - /** A shorthand for read() - */ - operator int() { - return read(); - } - -private: - port_t _port; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/PortInOut.h b/targetlibs/libmbed/PortInOut.h deleted file mode 100644 index cca755126..000000000 --- a/targetlibs/libmbed/PortInOut.h +++ /dev/null @@ -1,104 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTINOUT_H -#define MBED_PORTINOUT_H - -#include "platform.h" - -#if DEVICE_PORTINOUT - -#include "port_api.h" - -namespace mbed { - -/** A multiple pin digital in/out used to set/read multiple bi-directional pins - */ -class PortInOut { -public: - - /** Create an PortInOut, connected to the specified port - * - * @param port Port to connect to (Port0-Port5) - * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) - */ - PortInOut(PortName port, int mask = 0xFFFFFFFF) { - port_init(&_port, port, mask, PIN_INPUT); - } - - /** Write the value to the output port - * - * @param value An integer specifying a bit to write for every corresponding port pin - */ - void write(int value) { - port_write(&_port, value); - } - - /** Read the value currently output on the port - * - * @returns - * An integer with each bit corresponding to associated port pin setting - */ - int read() { - return port_read(&_port); - } - - /** Set as an output - */ - void output() { - port_dir(&_port, PIN_OUTPUT); - } - - /** Set as an input - */ - void input() { - port_dir(&_port, PIN_INPUT); - } - - /** Set the input pin mode - * - * @param mode PullUp, PullDown, PullNone, OpenDrain - */ - void mode(PinMode mode) { - port_mode(&_port, mode); - } - - /** A shorthand for write() - */ - PortInOut& operator= (int value) { - write(value); - return *this; - } - - PortInOut& operator= (PortInOut& rhs) { - write(rhs.read()); - return *this; - } - - /** A shorthand for read() - */ - operator int() { - return read(); - } - -private: - port_t _port; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/PortOut.h b/targetlibs/libmbed/PortOut.h deleted file mode 100644 index bab5fe0c6..000000000 --- a/targetlibs/libmbed/PortOut.h +++ /dev/null @@ -1,104 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTOUT_H -#define MBED_PORTOUT_H - -#include "platform.h" - -#if DEVICE_PORTOUT - -#include "port_api.h" - -namespace mbed { -/** A multiple pin digital out - * - * Example: - * @code - * // Toggle all four LEDs - * - * #include "mbed.h" - * - * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23 - * #define LED_MASK 0x00B40000 - * - * PortOut ledport(Port1, LED_MASK); - * - * int main() { - * while(1) { - * ledport = LED_MASK; - * wait(1); - * ledport = 0; - * wait(1); - * } - * } - * @endcode - */ -class PortOut { -public: - - /** Create an PortOut, connected to the specified port - * - * @param port Port to connect to (Port0-Port5) - * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) - */ - PortOut(PortName port, int mask = 0xFFFFFFFF) { - port_init(&_port, port, mask, PIN_OUTPUT); - } - - /** Write the value to the output port - * - * @param value An integer specifying a bit to write for every corresponding PortOut pin - */ - void write(int value) { - port_write(&_port, value); - } - - /** Read the value currently output on the port - * - * @returns - * An integer with each bit corresponding to associated PortOut pin setting - */ - int read() { - return port_read(&_port); - } - - /** A shorthand for write() - */ - PortOut& operator= (int value) { - write(value); - return *this; - } - - PortOut& operator= (PortOut& rhs) { - write(rhs.read()); - return *this; - } - - /** A shorthand for read() - */ - operator int() { - return read(); - } - -private: - port_t _port; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/PwmOut.h b/targetlibs/libmbed/PwmOut.h deleted file mode 100644 index 9e8c0bdf2..000000000 --- a/targetlibs/libmbed/PwmOut.h +++ /dev/null @@ -1,158 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PWMOUT_H -#define MBED_PWMOUT_H - -#include "platform.h" - -#if DEVICE_PWMOUT -#include "pwmout_api.h" - -namespace mbed { - -/** A pulse-width modulation digital output - * - * Example - * @code - * // Fade a led on. - * #include "mbed.h" - * - * PwmOut led(LED1); - * - * int main() { - * while(1) { - * led = led + 0.01; - * wait(0.2); - * if(led == 1.0) { - * led = 0; - * } - * } - * } - * @endcode - * - * @note - * On the LPC1768 and LPC2368, the PWMs all share the same - * period - if you change the period for one, you change it for all. - * Although routines that change the period maintain the duty cycle - * for its PWM, all other PWMs will require their duty cycle to be - * refreshed. - */ -class PwmOut { - -public: - - /** Create a PwmOut connected to the specified pin - * - * @param pin PwmOut pin to connect to - */ - PwmOut(PinName pin) { - pwmout_init(&_pwm, pin); - } - - /** Set the ouput duty-cycle, specified as a percentage (float) - * - * @param value A floating-point value representing the output duty-cycle, - * specified as a percentage. The value should lie between - * 0.0f (representing on 0%) and 1.0f (representing on 100%). - * Values outside this range will be saturated to 0.0f or 1.0f. - */ - void write(float value) { - pwmout_write(&_pwm, value); - } - - /** Return the current output duty-cycle setting, measured as a percentage (float) - * - * @returns - * A floating-point value representing the current duty-cycle being output on the pin, - * measured as a percentage. The returned value will lie between - * 0.0f (representing on 0%) and 1.0f (representing on 100%). - * - * @note - * This value may not match exactly the value set by a previous . - */ - float read() { - return pwmout_read(&_pwm); - } - - /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same. - * - * @note - * The resolution is currently in microseconds; periods smaller than this - * will be set to zero. - */ - void period(float seconds) { - pwmout_period(&_pwm, seconds); - } - - /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same. - */ - void period_ms(int ms) { - pwmout_period_ms(&_pwm, ms); - } - - /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same. - */ - void period_us(int us) { - pwmout_period_us(&_pwm, us); - } - - /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same. - */ - void pulsewidth(float seconds) { - pwmout_pulsewidth(&_pwm, seconds); - } - - /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same. - */ - void pulsewidth_ms(int ms) { - pwmout_pulsewidth_ms(&_pwm, ms); - } - - /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same. - */ - void pulsewidth_us(int us) { - pwmout_pulsewidth_us(&_pwm, us); - } - -#ifdef MBED_OPERATORS - /** A operator shorthand for write() - */ - PwmOut& operator= (float value) { - write(value); - return *this; - } - - PwmOut& operator= (PwmOut& rhs) { - write(rhs.read()); - return *this; - } - - /** An operator shorthand for read() - */ - operator float() { - return read(); - } -#endif - -protected: - pwmout_t _pwm; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/SPI.h b/targetlibs/libmbed/SPI.h deleted file mode 100644 index cdb773113..000000000 --- a/targetlibs/libmbed/SPI.h +++ /dev/null @@ -1,109 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SPI_H -#define MBED_SPI_H - -#include "platform.h" - -#if DEVICE_SPI - -#include "spi_api.h" - -namespace mbed { - -/** A SPI Master, used for communicating with SPI slave devices - * - * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz - * - * Most SPI devices will also require Chip Select and Reset signals. These - * can be controlled using pins - * - * Example: - * @code - * // Send a byte to a SPI slave, and record the response - * - * #include "mbed.h" - * - * SPI device(p5, p6, p7); // mosi, miso, sclk - * - * int main() { - * int response = device.write(0xFF); - * } - * @endcode - */ -class SPI { - -public: - - /** Create a SPI master connected to the specified pins - * - * Pin Options: - * (5, 6, 7) or (11, 12, 13) - * - * mosi or miso can be specfied as NC if not used - * - * @param mosi SPI Master Out, Slave In pin - * @param miso SPI Master In, Slave Out pin - * @param sclk SPI Clock pin - */ - SPI(PinName mosi, PinName miso, PinName sclk); - - /** Configure the data transmission format - * - * @param bits Number of bits per SPI frame (4 - 16) - * @param mode Clock polarity and phase mode (0 - 3) - * - * @code - * mode | POL PHA - * -----+-------- - * 0 | 0 0 - * 1 | 0 1 - * 2 | 1 0 - * 3 | 1 1 - * @endcode - */ - void format(int bits, int mode = 0); - - /** Set the spi bus clock frequency - * - * @param hz SCLK frequency in hz (default = 1MHz) - */ - void frequency(int hz = 1000000); - - /** Write to the SPI Slave and return the response - * - * @param value Data to be sent to the SPI slave - * - * @returns - * Response from the SPI slave - */ - virtual int write(int value); - -protected: - spi_t _spi; - - void aquire(void); - static SPI *_owner; - int _bits; - int _mode; - int _hz; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/SPISlave.h b/targetlibs/libmbed/SPISlave.h deleted file mode 100644 index d06c7e1b4..000000000 --- a/targetlibs/libmbed/SPISlave.h +++ /dev/null @@ -1,126 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SPISLAVE_H -#define MBED_SPISLAVE_H - -#include "platform.h" - -#if DEVICE_SPISLAVE - -#include "spi_api.h" - -namespace mbed { - -/** A SPI slave, used for communicating with a SPI Master device - * - * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz - * - * Example: - * @code - * // Reply to a SPI master as slave - * - * #include "mbed.h" - * - * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel - * - * int main() { - * device.reply(0x00); // Prime SPI with first reply - * while(1) { - * if(device.receive()) { - * int v = device.read(); // Read byte from master - * v = (v + 1) % 0x100; // Add one to it, modulo 256 - * device.reply(v); // Make this the next reply - * } - * } - * } - * @endcode - */ -class SPISlave { - -public: - - /** Create a SPI slave connected to the specified pins - * - * Pin Options: - * (5, 6, 7i, 8) or (11, 12, 13, 14) - * - * mosi or miso can be specfied as NC if not used - * - * @param mosi SPI Master Out, Slave In pin - * @param miso SPI Master In, Slave Out pin - * @param sclk SPI Clock pin - * @param ssel SPI chip select pin - * @param name (optional) A string to identify the object - */ - SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel); - - /** Configure the data transmission format - * - * @param bits Number of bits per SPI frame (4 - 16) - * @param mode Clock polarity and phase mode (0 - 3) - * - * @code - * mode | POL PHA - * -----+-------- - * 0 | 0 0 - * 1 | 0 1 - * 2 | 1 0 - * 3 | 1 1 - * @endcode - */ - void format(int bits, int mode = 0); - - /** Set the spi bus clock frequency - * - * @param hz SCLK frequency in hz (default = 1MHz) - */ - void frequency(int hz = 1000000); - - /** Polls the SPI to see if data has been received - * - * @returns - * 0 if no data, - * 1 otherwise - */ - int receive(void); - - /** Retrieve data from receive buffer as slave - * - * @returns - * the data in the receive buffer - */ - int read(void); - - /** Fill the transmission buffer with the value to be written out - * as slave on the next received message from the master. - * - * @param value the data to be transmitted next - */ - void reply(int value); - -protected: - spi_t _spi; - - int _bits; - int _mode; - int _hz; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/Serial.h b/targetlibs/libmbed/Serial.h deleted file mode 100644 index 7c7b39e84..000000000 --- a/targetlibs/libmbed/Serial.h +++ /dev/null @@ -1,138 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SERIAL_H -#define MBED_SERIAL_H - -#include "platform.h" - -#if DEVICE_SERIAL - -#include "Stream.h" -#include "FunctionPointer.h" -#include "serial_api.h" - -namespace mbed { - -/** A serial port (UART) for communication with other serial devices - * - * Can be used for Full Duplex communication, or Simplex by specifying - * one pin as NC (Not Connected) - * - * Example: - * @code - * // Print "Hello World" to the PC - * - * #include "mbed.h" - * - * Serial pc(USBTX, USBRX); - * - * int main() { - * pc.printf("Hello World\n"); - * } - * @endcode - */ -class Serial : public Stream { - -public: - /** Create a Serial port, connected to the specified transmit and receive pins - * - * @param tx Transmit pin - * @param rx Receive pin - * - * @note - * Either tx or rx may be specified as NC if unused - */ - Serial(PinName tx, PinName rx, const char *name=NULL); - - /** Set the baud rate of the serial port - * - * @param baudrate The baudrate of the serial port (default = 9600). - */ - void baud(int baudrate); - - enum Parity { - None = 0, - Odd, - Even, - Forced1, - Forced0 - }; - - enum IrqType { - RxIrq = 0, - TxIrq - }; - - /** Set the transmission format used by the Serial port - * - * @param bits The number of bits in a word (5-8; default = 8) - * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) - * @param stop The number of stop bits (1 or 2; default = 1) - */ - void format(int bits = 8, Parity parity=Serial::None, int stop_bits=1); - - /** Determine if there is a character available to read - * - * @returns - * 1 if there is a character available to read, - * 0 otherwise - */ - int readable(); - - /** Determine if there is space available to write a character - * - * @returns - * 1 if there is space to write a character, - * 0 otherwise - */ - int writeable(); - - /** Attach a function to call whenever a serial interrupt is generated - * - * @param fptr A pointer to a void function, or 0 to set as none - * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) - */ - void attach(void (*fptr)(void), IrqType type=RxIrq); - - /** Attach a member function to call whenever a serial interrupt is generated - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) - */ - template - void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { - if((mptr != NULL) && (tptr != NULL)) { - _irq[type].attach(tptr, mptr); - serial_irq_set(&_serial, (SerialIrq)type, 1); - } - } - - static void _irq_handler(uint32_t id, SerialIrq irq_type); - -protected: - virtual int _getc(); - virtual int _putc(int c); - - serial_t _serial; - FunctionPointer _irq[2]; -}; - -} // namespace mbed - -#endif - -#endif diff --git a/targetlibs/libmbed/Stream.h b/targetlibs/libmbed/Stream.h deleted file mode 100644 index 8b1a56879..000000000 --- a/targetlibs/libmbed/Stream.h +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_STREAM_H -#define MBED_STREAM_H - -#include "platform.h" -#include "FileLike.h" - -namespace mbed { - -class Stream : public FileLike { - -public: - Stream(const char *name=NULL); - virtual ~Stream(); - - int putc(int c); - int puts(const char *s); - int getc(); - char *gets(char *s, int size); - int printf(const char* format, ...); - int scanf(const char* format, ...); - - operator std::FILE*() {return _file;} - -protected: - virtual int close(); - virtual ssize_t write(const void* buffer, size_t length); - virtual ssize_t read(void* buffer, size_t length); - virtual off_t lseek(off_t offset, int whence); - virtual int isatty(); - virtual int fsync(); - virtual off_t flen(); - - virtual int _putc(int c) = 0; - virtual int _getc() = 0; - - std::FILE *_file; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/Ticker.h b/targetlibs/libmbed/Ticker.h deleted file mode 100644 index 73da8a5fb..000000000 --- a/targetlibs/libmbed/Ticker.h +++ /dev/null @@ -1,117 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TICKER_H -#define MBED_TICKER_H - -#include "TimerEvent.h" -#include "FunctionPointer.h" - -namespace mbed { - -/** A Ticker is used to call a function at a recurring interval - * - * You can use as many seperate Ticker objects as you require. - * - * Example: - * @code - * // Toggle the blinking led after 5 seconds - * - * #include "mbed.h" - * - * Ticker timer; - * DigitalOut led1(LED1); - * DigitalOut led2(LED2); - * - * int flip = 0; - * - * void attime() { - * flip = !flip; - * } - * - * int main() { - * timer.attach(&attime, 5); - * while(1) { - * if(flip == 0) { - * led1 = !led1; - * } else { - * led2 = !led2; - * } - * wait(0.2); - * } - * } - * @endcode - */ -class Ticker : public TimerEvent { - -public: - - /** Attach a function to be called by the Ticker, specifiying the interval in seconds - * - * @param fptr pointer to the function to be called - * @param t the time between calls in seconds - */ - void attach(void (*fptr)(void), float t) { - attach_us(fptr, t * 1000000.0f); - } - - /** Attach a member function to be called by the Ticker, specifiying the interval in seconds - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - * @param t the time between calls in seconds - */ - template - void attach(T* tptr, void (T::*mptr)(void), float t) { - attach_us(tptr, mptr, t * 1000000.0f); - } - - /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds - * - * @param fptr pointer to the function to be called - * @param t the time between calls in micro-seconds - */ - void attach_us(void (*fptr)(void), unsigned int t) { - _function.attach(fptr); - setup(t); - } - - /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds - * - * @param tptr pointer to the object to call the member function on - * @param mptr pointer to the member function to be called - * @param t the time between calls in micro-seconds - */ - template - void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) { - _function.attach(tptr, mptr); - setup(t); - } - - /** Detach the function - */ - void detach(); - -protected: - void setup(unsigned int t); - virtual void handler(); - - unsigned int _delay; - FunctionPointer _function; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/Timeout.h b/targetlibs/libmbed/Timeout.h deleted file mode 100644 index e145d9a77..000000000 --- a/targetlibs/libmbed/Timeout.h +++ /dev/null @@ -1,59 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TIMEOUT_H -#define MBED_TIMEOUT_H - -#include "Ticker.h" - -namespace mbed { - -/** A Timeout is used to call a function at a point in the future - * - * You can use as many seperate Timeout objects as you require. - * - * Example: - * @code - * // Blink until timeout. - * - * #include "mbed.h" - * - * Timeout timeout; - * DigitalOut led(LED1); - * - * int on = 1; - * - * void attimeout() { - * on = 0; - * } - * - * int main() { - * timeout.attach(&attimeout, 5); - * while(on) { - * led = !led; - * wait(0.2); - * } - * } - * @endcode - */ -class Timeout : public Ticker { - -protected: - virtual void handler(); -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/Timer.h b/targetlibs/libmbed/Timer.h deleted file mode 100644 index aedf0377e..000000000 --- a/targetlibs/libmbed/Timer.h +++ /dev/null @@ -1,88 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TIMER_H -#define MBED_TIMER_H - -#include "platform.h" - -namespace mbed { - -/** A general purpose timer - * - * Example: - * @code - * // Count the time to toggle a LED - * - * #include "mbed.h" - * - * Timer timer; - * DigitalOut led(LED1); - * int begin, end; - * - * int main() { - * timer.start(); - * begin = timer.read_us(); - * led = !led; - * end = timer.read_us(); - * printf("Toggle the led takes %d us", end - begin); - * } - * @endcode - */ -class Timer { - -public: - Timer(); - - /** Start the timer - */ - void start(); - - /** Stop the timer - */ - void stop(); - - /** Reset the timer to 0. - * - * If it was already counting, it will continue - */ - void reset(); - - /** Get the time passed in seconds - */ - float read(); - - /** Get the time passed in mili-seconds - */ - int read_ms(); - - /** Get the time passed in micro-seconds - */ - int read_us(); - -#ifdef MBED_OPERATORS - operator float(); -#endif - -protected: - int slicetime(); - int _running; // whether the timer is running - unsigned int _start; // the start time of the latest slice - int _time; // any accumulated time from previous slices -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/TimerEvent.h b/targetlibs/libmbed/TimerEvent.h deleted file mode 100644 index 81e47e114..000000000 --- a/targetlibs/libmbed/TimerEvent.h +++ /dev/null @@ -1,52 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TIMEREVENT_H -#define MBED_TIMEREVENT_H - -#include "us_ticker_api.h" - -namespace mbed { - -/** Base abstraction for timer interrupts -*/ -class TimerEvent { -public: - TimerEvent(); - - /** The handler registered with the underlying timer interrupt - */ - static void irq(uint32_t id); - - /** Destruction removes it... - */ - virtual ~TimerEvent(); - -protected: - // The handler called to service the timer event of the derived class - virtual void handler() = 0; - - // insert in to linked list - void insert(unsigned int timestamp); - - // remove from linked list, if in it - void remove(); - - ticker_event_t event; -}; - -} // namespace mbed - -#endif diff --git a/targetlibs/libmbed/analogin_api.h b/targetlibs/libmbed/analogin_api.h deleted file mode 100644 index 98d02c1b8..000000000 --- a/targetlibs/libmbed/analogin_api.h +++ /dev/null @@ -1,39 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ANALOGIN_API_H -#define MBED_ANALOGIN_API_H - -#include "device.h" - -#if DEVICE_ANALOGIN - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct analogin_s analogin_t; - -void analogin_init (analogin_t *obj, PinName pin); -float analogin_read (analogin_t *obj); -uint16_t analogin_read_u16(analogin_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/analogout_api.h b/targetlibs/libmbed/analogout_api.h deleted file mode 100644 index 97a201376..000000000 --- a/targetlibs/libmbed/analogout_api.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ANALOGOUT_API_H -#define MBED_ANALOGOUT_API_H - -#include "device.h" - -#if DEVICE_ANALOGOUT - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct dac_s dac_t; - -void analogout_init (dac_t *obj, PinName pin); -void analogout_free (dac_t *obj); -void analogout_write (dac_t *obj, float value); -void analogout_write_u16(dac_t *obj, uint16_t value); -float analogout_read (dac_t *obj); -uint16_t analogout_read_u16 (dac_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/can_api.h b/targetlibs/libmbed/can_api.h deleted file mode 100644 index b681cae90..000000000 --- a/targetlibs/libmbed/can_api.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_CAN_API_H -#define MBED_CAN_API_H - -#include "device.h" - -#if DEVICE_CAN - -#include "PinNames.h" -#include "PeripheralNames.h" -#include "can_helper.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct can_s can_t; - -void can_init (can_t *obj, PinName rd, PinName td); -void can_free (can_t *obj); -int can_frequency(can_t *obj, int hz); -int can_write (can_t *obj, CAN_Message, int cc); -int can_read (can_t *obj, CAN_Message *msg); -void can_reset (can_t *obj); -unsigned char can_rderror (can_t *obj); -unsigned char can_tderror (can_t *obj); -void can_monitor (can_t *obj, int silent); - -#ifdef __cplusplus -}; -#endif - -#endif // MBED_CAN_API_H - -#endif diff --git a/targetlibs/libmbed/can_helper.h b/targetlibs/libmbed/can_helper.h deleted file mode 100644 index 45aa231dc..000000000 --- a/targetlibs/libmbed/can_helper.h +++ /dev/null @@ -1,52 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_CAN_HELPER_H -#define MBED_CAN_HELPER_H - -#if DEVICE_CAN - -#ifdef __cplusplus -extern "C" { -#endif - -enum CANFormat { - CANStandard = 0, - CANExtended = 1 -}; -typedef enum CANFormat CANFormat; - -enum CANType { - CANData = 0, - CANRemote = 1 -}; -typedef enum CANType CANType; - -struct CAN_Message { - unsigned int id; // 29 bit identifier - unsigned char data[8]; // Data field - unsigned char len; // Length of data field in bytes - CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER - CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME -}; -typedef struct CAN_Message CAN_Message; - -#ifdef __cplusplus -}; -#endif - -#endif - -#endif // MBED_CAN_HELPER_H diff --git a/targetlibs/libmbed/error.h b/targetlibs/libmbed/error.h deleted file mode 100644 index d8f576009..000000000 --- a/targetlibs/libmbed/error.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ERROR_H -#define MBED_ERROR_H - -/** To generate a fatal compile-time error, you can use the pre-processor #error directive. - * - * @code - * #error "That shouldn't have happened!" - * @endcode - * - * If the compiler evaluates this line, it will report the error and stop the compile. - * - * For example, you could use this to check some user-defined compile-time variables: - * - * @code - * #define NUM_PORTS 7 - * #if (NUM_PORTS > 4) - * #error "NUM_PORTS must be less than 4" - * #endif - * @endcode - * - * Reporting Run-Time Errors: - * To generate a fatal run-time error, you can use the mbed error() function. - * - * @code - * error("That shouldn't have happened!"); - * @endcode - * - * If the mbed running the program executes this function, it will print the - * message via the USB serial port, and then die with the blue lights of death! - * - * The message can use printf-style formatting, so you can report variables in the - * message too. For example, you could use this to check a run-time condition: - * - * @code - * if(x >= 5) { - * error("expected x to be less than 5, but got %d", x); - * } - * #endcode - */ - -#include -#include "device.h" - -#ifdef DEVICE_STDIO_MESSAGES - #include - #define error(...) (fprintf(stderr, __VA_ARGS__), exit(1)) -#else - #define error(...) (exit(1)) -#endif - -#endif diff --git a/targetlibs/libmbed/ethernet_api.h b/targetlibs/libmbed/ethernet_api.h deleted file mode 100644 index 4cae77e13..000000000 --- a/targetlibs/libmbed/ethernet_api.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ETHERNET_API_H -#define MBED_ETHERNET_API_H - -#include "device.h" - -#if DEVICE_ETHERNET - -#ifdef __cplusplus -extern "C" { -#endif - -// Connection constants - -int ethernet_init(void); -void ethernet_free(void); - -// write size bytes from data to ethernet buffer -// return num bytes written -// or -1 if size is too big -int ethernet_write(const char *data, int size); - -// send ethernet write buffer, returning the packet size sent -int ethernet_send(void); - -// recieve from ethernet buffer, returning packet size, or 0 if no packet -int ethernet_receive(void); - -// read size bytes in to data, return actual num bytes read (0..size) -// if data == NULL, throw the bytes away -int ethernet_read(char *data, int size); - -// get the ethernet address -void ethernet_address(char *mac); - -// see if the link is up -int ethernet_link(void); - -// force link settings -void ethernet_set_link(int speed, int duplex); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/targetlibs/libmbed/gpio_api.h b/targetlibs/libmbed/gpio_api.h deleted file mode 100644 index e254893a6..000000000 --- a/targetlibs/libmbed/gpio_api.h +++ /dev/null @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_API_H -#define MBED_GPIO_API_H - -#include "device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Set the given pin as GPIO - * @param pin The pin to be set as GPIO - * @return The GPIO port mask for this pin - **/ -uint32_t gpio_set(PinName pin); - -/* GPIO object */ -void gpio_init(gpio_t *obj, PinName pin, PinDirection direction); -void gpio_mode(gpio_t *obj, PinMode mode); -void gpio_dir (gpio_t *obj, PinDirection direction); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/gpio_irq_api.h b/targetlibs/libmbed/gpio_irq_api.h deleted file mode 100644 index 2eadb4f58..000000000 --- a/targetlibs/libmbed/gpio_irq_api.h +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_IRQ_API_H -#define MBED_GPIO_IRQ_API_H - -#include "device.h" - -#if DEVICE_INTERRUPTIN - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - IRQ_NONE, - IRQ_RISE, - IRQ_FALL -} gpio_irq_event; - -typedef struct gpio_irq_s gpio_irq_t; - -typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id); -void gpio_irq_free(gpio_irq_t *obj); -void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/i2c_api.h b/targetlibs/libmbed/i2c_api.h deleted file mode 100644 index f0bbaaef4..000000000 --- a/targetlibs/libmbed/i2c_api.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_I2C_API_H -#define MBED_I2C_API_H - -#include "device.h" - -#if DEVICE_I2C - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct i2c_s i2c_t; - -void i2c_init (i2c_t *obj, PinName sda, PinName scl); -void i2c_frequency (i2c_t *obj, int hz); -int i2c_start (i2c_t *obj); -void i2c_stop (i2c_t *obj); -int i2c_read (i2c_t *obj, int address, char *data, int length, int stop); -int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop); -void i2c_reset (i2c_t *obj); -int i2c_byte_read (i2c_t *obj, int last); -int i2c_byte_write (i2c_t *obj, int data); - -#if DEVICE_I2CSLAVE -void i2c_slave_mode (i2c_t *obj, int enable_slave); -int i2c_slave_receive(i2c_t *obj); -int i2c_slave_read (i2c_t *obj, char *data, int length); -int i2c_slave_write (i2c_t *obj, const char *data, int length); -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask); -#endif - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/mbed.h b/targetlibs/libmbed/mbed.h deleted file mode 100644 index bba24a76d..000000000 --- a/targetlibs/libmbed/mbed.h +++ /dev/null @@ -1,65 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_H -#define MBED_H - -#define MBED_LIBRARY_VERSION 30 - -#include "platform.h" - -// Useful C libraries -#include -#include - -// mbed Debug libraries -#include "error.h" -#include "mbed_interface.h" - -// mbed Peripheral components -#include "DigitalIn.h" -#include "DigitalOut.h" -#include "DigitalInOut.h" -#include "BusIn.h" -#include "BusOut.h" -#include "BusInOut.h" -#include "PortIn.h" -#include "PortInOut.h" -#include "PortOut.h" -#include "AnalogIn.h" -#include "AnalogOut.h" -#include "PwmOut.h" -#include "Serial.h" -#include "SPI.h" -#include "SPISlave.h" -#include "I2C.h" -#include "I2CSlave.h" -#include "Ethernet.h" -#include "CAN.h" - -// mbed Internal components -#include "Timer.h" -#include "Ticker.h" -#include "Timeout.h" -#include "LocalFileSystem.h" -#include "InterruptIn.h" -#include "wait_api.h" -#include "sleep_api.h" -#include "rtc_time.h" - -using namespace mbed; -using namespace std; - -#endif diff --git a/targetlibs/libmbed/mbed_debug.h b/targetlibs/libmbed/mbed_debug.h deleted file mode 100644 index 48892c517..000000000 --- a/targetlibs/libmbed/mbed_debug.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEBUG_H -#define MBED_DEBUG_H -#include "device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef DEVICE_STDIO_MESSAGES -#include -#include - -/** Output a debug message - * - * @param format printf-style format string, followed by variables - */ -static inline void debug(const char *format, ...) { - va_list args; - va_start(args, format); - vfprintf(stderr, format, args); - va_end(args); -} - -/** Conditionally output a debug message - * - * NOTE: If the condition is constant false (!= 1) and the compiler optimization - * level is greater than 0, then the whole function will be compiled away. - * - * @param condition output only if condition is true (== 1) - * @param format printf-style format string, followed by variables - */ -static inline void debug_if(int condition, const char *format, ...) { - if (condition == 1) { - va_list args; - va_start(args, format); - vfprintf(stderr, format, args); - va_end(args); - } -} - -#else -static inline void debug(const char *format, ...) {} -static inline void debug_if(int condition, const char *format, ...) {} - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/mbed_interface.h b/targetlibs/libmbed/mbed_interface.h deleted file mode 100644 index d51b7f48f..000000000 --- a/targetlibs/libmbed/mbed_interface.h +++ /dev/null @@ -1,101 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_INTERFACE_H -#define MBED_INTERFACE_H - -#include "device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if DEVICE_SEMIHOST - -/** Functions to control the mbed interface - * - * mbed Microcontrollers have a built-in interface to provide functionality such as - * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file - * system. These functions provide means to control the interface suing semihost - * calls it supports. - */ - -/** Determine whether the mbed interface is connected, based on whether debug is enabled - * - * @returns - * 1 if interface is connected, - * 0 otherwise - */ -int mbed_interface_connected(void); - -/** Instruct the mbed interface to reset, as if the reset button had been pressed - * - * @returns - * 1 if successful, - * 0 otherwise (e.g. interface not present) - */ -int mbed_interface_reset(void); - -/** This will disconnect the debug aspect of the interface, so semihosting will be disabled. - * The interface will still support the USB serial aspect - * - * @returns - * 0 if successful, - * -1 otherwise (e.g. interface not present) - */ -int mbed_interface_disconnect(void); - -/** This will disconnect the debug aspect of the interface, and if the USB cable is not - * connected, also power down the interface. If the USB cable is connected, the interface - * will remain powered up and visible to the host - * - * @returns - * 0 if successful, - * -1 otherwise (e.g. interface not present) - */ -int mbed_interface_powerdown(void); - -/** This returns a string containing the 32-character UID of the mbed interface - * This is a weak function that can be overwritten if required - * - * @param uid A 33-byte array to write the null terminated 32-byte string - * - * @returns - * 0 if successful, - * -1 otherwise (e.g. interface not present) - */ -int mbed_interface_uid(char *uid); - -#endif - -/** This returns a unique 6-byte MAC address, based on the interface UID - * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00) - * - * This is a weak function that can be overwritten if you want to provide your own mechanism to - * provide a MAC address. - * - * @param mac A 6-byte array to write the MAC address - */ -void mbed_mac_address(char *mac); - -/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence - */ -void mbed_die(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/pinmap.h b/targetlibs/libmbed/pinmap.h deleted file mode 100644 index 0482282eb..000000000 --- a/targetlibs/libmbed/pinmap.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINMAP_H -#define MBED_PINMAP_H - -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - int peripheral; - int function; -} PinMap; - -void pin_function(PinName pin, int function); -void pin_mode (PinName pin, PinMode mode); - -uint32_t pinmap_peripheral(PinName pin, const PinMap* map); -uint32_t pinmap_merge (uint32_t a, uint32_t b); -void pinmap_pinout (PinName pin, const PinMap *map); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/platform.h b/targetlibs/libmbed/platform.h deleted file mode 100644 index 85e44e57b..000000000 --- a/targetlibs/libmbed/platform.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PLATFORM_H -#define MBED_PLATFORM_H - -#define MBED_OPERATORS 1 - -#include "device.h" -#include "PinNames.h" -#include "PeripheralNames.h" - -#include -#include -#include -#include - -#endif diff --git a/targetlibs/libmbed/port_api.h b/targetlibs/libmbed/port_api.h deleted file mode 100644 index f687cfe89..000000000 --- a/targetlibs/libmbed/port_api.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTMAP_H -#define MBED_PORTMAP_H - -#include "device.h" - -#if DEVICE_PORTIN || DEVICE_PORTOUT - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct port_s port_t; - -PinName port_pin(PortName port, int pin_n); - -void port_init (port_t *obj, PortName port, int mask, PinDirection dir); -void port_mode (port_t *obj, PinMode mode); -void port_dir (port_t *obj, PinDirection dir); -void port_write(port_t *obj, int value); -int port_read (port_t *obj); - -#ifdef __cplusplus -} -#endif -#endif - -#endif diff --git a/targetlibs/libmbed/pwmout_api.h b/targetlibs/libmbed/pwmout_api.h deleted file mode 100644 index 6557fcdc4..000000000 --- a/targetlibs/libmbed/pwmout_api.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PWMOUT_API_H -#define MBED_PWMOUT_API_H - -#include "device.h" - -#if DEVICE_PWMOUT - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct pwmout_s pwmout_t; - -void pwmout_init (pwmout_t* obj, PinName pin); -void pwmout_free (pwmout_t* obj); - -void pwmout_write (pwmout_t* obj, float percent); -float pwmout_read (pwmout_t* obj); - -void pwmout_period (pwmout_t* obj, float seconds); -void pwmout_period_ms (pwmout_t* obj, int ms); -void pwmout_period_us (pwmout_t* obj, int us); - -void pwmout_pulsewidth (pwmout_t* obj, float seconds); -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms); -void pwmout_pulsewidth_us(pwmout_t* obj, int us); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/rtc_api.h b/targetlibs/libmbed/rtc_api.h deleted file mode 100644 index 663f8884f..000000000 --- a/targetlibs/libmbed/rtc_api.h +++ /dev/null @@ -1,42 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_RTC_API_H -#define MBED_RTC_API_H - -#include "device.h" - -#if DEVICE_RTC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void rtc_init(void); -void rtc_free(void); -int rtc_isenabled(void); - -time_t rtc_read(void); -void rtc_write(time_t t); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/rtc_time.h b/targetlibs/libmbed/rtc_time.h deleted file mode 100644 index 59ab8fd36..000000000 --- a/targetlibs/libmbed/rtc_time.h +++ /dev/null @@ -1,74 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** Implementation of the C time.h functions - * - * Provides mechanisms to set and read the current time, based - * on the microcontroller Real-Time Clock (RTC), plus some - * standard C manipulation and formating functions. - * - * Example: - * @code - * #include "mbed.h" - * - * int main() { - * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37 - * - * while(1) { - * time_t seconds = time(NULL); - * - * printf("Time as seconds since January 1, 1970 = %d\n", seconds); - * - * printf("Time as a basic string = %s", ctime(&seconds)); - * - * char buffer[32]; - * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds)); - * printf("Time as a custom formatted string = %s", buffer); - * - * wait(1); - * } - * } - * @endcode - */ - -/** Set the current time - * - * Initialises and sets the time of the microcontroller Real-Time Clock (RTC) - * to the time represented by the number of seconds since January 1, 1970 - * (the UNIX timestamp). - * - * @param t Number of seconds since January 1, 1970 (the UNIX timestamp) - * - * Example: - * @code - * #include "mbed.h" - * - * int main() { - * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37 - * } - * @endcode - */ -void set_time(time_t t); - -#ifdef __cplusplus -} -#endif diff --git a/targetlibs/libmbed/semihost_api.h b/targetlibs/libmbed/semihost_api.h deleted file mode 100644 index 279f67160..000000000 --- a/targetlibs/libmbed/semihost_api.h +++ /dev/null @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SEMIHOST_H -#define MBED_SEMIHOST_H - -#include "device.h" -#include "toolchain.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if DEVICE_SEMIHOST - -#ifndef __CC_ARM - -#if defined(__ICCARM__) -inline int __semihost(int reason, const void *arg) { - return __semihosting(reason, (void*)arg); -} -#else - -#ifdef __thumb__ -# define AngelSWI 0xAB -# define AngelSWIInsn "bkpt" -# define AngelSWIAsm bkpt -#else -# define AngelSWI 0x123456 -# define AngelSWIInsn "swi" -# define AngelSWIAsm swi -#endif - -static inline int __semihost(int reason, const void *arg) { - int value; - - asm volatile ( - "mov r0, %1" "\n\t" - "mov r1, %2" "\n\t" - AngelSWIInsn " %a3" "\n\t" - "mov %0, r0" - : "=r" (value) /* output operands */ - : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */ - : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */ - ); - - return value; -} -#endif -#endif - -#if DEVICE_LOCALFILESYSTEM -FILEHANDLE semihost_open(const char* name, int openmode); -int semihost_close (FILEHANDLE fh); -int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode); -int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode); -int semihost_ensure(FILEHANDLE fh); -long semihost_flen (FILEHANDLE fh); -int semihost_seek (FILEHANDLE fh, long position); -int semihost_istty (FILEHANDLE fh); - -int semihost_remove(const char *name); -int semihost_rename(const char *old_name, const char *new_name); -#endif - -int semihost_uid(char *uid); -int semihost_reset(void); -int semihost_vbus(void); -int semihost_powerdown(void); -int semihost_exit(void); - -int semihost_connected(void); -int semihost_disabledebug(void); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/serial_api.h b/targetlibs/libmbed/serial_api.h deleted file mode 100644 index c93fc347c..000000000 --- a/targetlibs/libmbed/serial_api.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SERIAL_API_H -#define MBED_SERIAL_API_H - -#include "device.h" - -#if DEVICE_SERIAL - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ParityNone = 0, - ParityOdd = 1, - ParityEven = 2, - ParityForced1 = 3, - ParityForced0 = 4 -} SerialParity; - -typedef enum { - RxIrq, - TxIrq -} SerialIrq; - -typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event); - -typedef struct serial_s serial_t; - -void serial_init (serial_t *obj, PinName tx, PinName rx); -void serial_free (serial_t *obj); -void serial_baud (serial_t *obj, int baudrate); -void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits); - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id); -void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable); - -int serial_getc (serial_t *obj); -void serial_putc (serial_t *obj, int c); -int serial_readable (serial_t *obj); -int serial_writable (serial_t *obj); -void serial_clear (serial_t *obj); - -void serial_pinout_tx(PinName tx); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/sleep_api.h b/targetlibs/libmbed/sleep_api.h deleted file mode 100644 index c8cf3b6f8..000000000 --- a/targetlibs/libmbed/sleep_api.h +++ /dev/null @@ -1,64 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SLEEP_API_H -#define MBED_SLEEP_API_H - -#include "device.h" - -#if DEVICE_SLEEP - -#ifdef __cplusplus -extern "C" { -#endif - -/** Send the microcontroller to sleep - * - * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the - * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates - * dynamic power used by the processor, memory systems and buses. The processor, peripheral and - * memory state are maintained, and the peripherals continue to work and can generate interrupts. - * - * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. - * - * @note - * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. - * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be - * able to access the LocalFileSystem - */ -void sleep(void); - -/** Send the microcontroller to deep sleep - * - * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode - * has the same sleep features as sleep plus it powers down peripherals and clocks. All state - * is still maintained. - * - * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. - * - * @note - * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. - * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be - * able to access the LocalFileSystem - */ -void deepsleep(void); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/spi_api.h b/targetlibs/libmbed/spi_api.h deleted file mode 100644 index 7553dc1e3..000000000 --- a/targetlibs/libmbed/spi_api.h +++ /dev/null @@ -1,45 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_SPI_API_H -#define MBED_SPI_API_H - -#include "device.h" - -#if DEVICE_SPI - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct spi_s spi_t; - -void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); -void spi_free (spi_t *obj); -void spi_format (spi_t *obj, int bits, int mode, int slave); -void spi_frequency (spi_t *obj, int hz); -int spi_master_write (spi_t *obj, int value); -int spi_slave_receive(spi_t *obj); -int spi_slave_read (spi_t *obj); -void spi_slave_write (spi_t *obj, int value); -int spi_busy (spi_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/targetlibs/libmbed/toolchain.h b/targetlibs/libmbed/toolchain.h deleted file mode 100644 index 69a4ddd87..000000000 --- a/targetlibs/libmbed/toolchain.h +++ /dev/null @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TOOLCHAIN_H -#define MBED_TOOLCHAIN_H - -#if defined(TOOLCHAIN_ARM) || defined(TOOLCHAIN_uARM) -#include -#endif - -#ifndef FILEHANDLE -typedef int FILEHANDLE; -#endif - -#if defined (__ICCARM__) -# define WEAK __weak -# define PACKED __packed -#else -# define WEAK __attribute__((weak)) -# define PACKED __attribute__((packed)) -#endif - -#endif diff --git a/targetlibs/libmbed/us_ticker_api.h b/targetlibs/libmbed/us_ticker_api.h deleted file mode 100644 index 703f10012..000000000 --- a/targetlibs/libmbed/us_ticker_api.h +++ /dev/null @@ -1,49 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_US_TICKER_API_H -#define MBED_US_TICKER_API_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -uint32_t us_ticker_read(void); - -typedef void (*ticker_event_handler)(uint32_t id); -void us_ticker_set_handler(ticker_event_handler handler); - -typedef struct ticker_event_s { - uint32_t timestamp; - uint32_t id; - struct ticker_event_s *next; -} ticker_event_t; - -void us_ticker_init(void); -void us_ticker_set_interrupt(unsigned int timestamp); -void us_ticker_disable_interrupt(void); -void us_ticker_clear_interrupt(void); -void us_ticker_irq_handler(void); - -void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id); -void us_ticker_remove_event(ticker_event_t *obj); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targetlibs/libmbed/wait_api.h b/targetlibs/libmbed/wait_api.h deleted file mode 100644 index 03c27141e..000000000 --- a/targetlibs/libmbed/wait_api.h +++ /dev/null @@ -1,66 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_WAIT_API_H -#define MBED_WAIT_API_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** Generic wait functions. - * - * These provide simple NOP type wait capabilities. - * - * Example: - * @code - * #include "mbed.h" - * - * DigitalOut heartbeat(LED1); - * - * int main() { - * while (1) { - * heartbeat = 1; - * wait(0.5); - * heartbeat = 0; - * wait(0.5); - * } - * } - */ - -/** Waits for a number of seconds, with microsecond resolution (within - * the accuracy of single precision floating point). - * - * @param s number of seconds to wait - */ -void wait(float s); - -/** Waits a number of milliseconds. - * - * @param ms the whole number of milliseconds to wait - */ -void wait_ms(int ms); - -/** Waits a number of microseconds. - * - * @param us the whole number of microseconds to wait - */ -void wait_us(int us); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/esp8266/README_flash.txt b/targets/esp8266/README_flash.txt index 248ec70cf..82c896dc6 100644 --- a/targets/esp8266/README_flash.txt +++ b/targets/esp8266/README_flash.txt @@ -2,14 +2,18 @@ How to flash Espruino esp8266 ============================= *** To flash a 512KB esp8266 (e.g. esp-01) using the serial port use: -esptool.py --port [/dev/ttyUSB0|COM1] --baud 460800 write_flash \ +esptool.py --port [/dev/ttyUSB0|COM1] --baud 115200 write_flash \ --flash_freq 40m --flash_mode qio --flash_size 4m \ - 0x0000 "boot_v1.4(b1).bin" 0x1000 espruino_esp8266_user1.bin 0x7E000 blank.bin + 0x0000 "boot_v1.6.bin" 0x1000 espruino_esp8266_user1.bin + 0x7C000 esp_init_data_default.bin 0x7E000 blank.bin *** To flash a 4MB esp8266 (e.g. esp-12) using the serial port use: -esptool.py --port [/dev/ttyUSB0|COM1] --baud 460800 write_flash \ +esptool.py --port [/dev/ttyUSB0|COM1] --baud 115200 write_flash \ --flash_freq 80m --flash_mode qio --flash_size 32m \ - 0x0000 "boot_v1.4(b1).bin" 0x1000 espruino_esp8266_user1.bin 0x37E000 blank.bin + 0x0000 "boot_v1.6.bin" 0x1000 espruino_esp8266_user1.bin \ + 0x3FC000 esp_init_data_default.bin 0x37E000 blank.bin + +For 1MB flash use 0xFC000/0xFE000 and for 2MB flash use 0x1FC000/0x1FE000 on the last line. *** Get esptool.py from https://github.com/themadinventor/esptool diff --git a/targets/esp8266/i2c_master.c b/targets/esp8266/i2c_master.c index 004b82662..c82cc770d 100644 --- a/targets/esp8266/i2c_master.c +++ b/targets/esp8266/i2c_master.c @@ -73,10 +73,10 @@ i2c_master_setDC(uint8 SDA, uint8 SCL) m_nLastSCL = SCL; //I2C_MASTER_SDA_SCL(SDA, SCL); - GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, SDA< ESP8266: jshPinSetValue pin=%d, value=%d\n", pin, value); - GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, (value&1)< jshI2CSetup: SCL=%d SDA=%d bitrate=%d\n", // info->pinSCL, info->pinSDA, info->bitrate); if (device != EV_I2C1) { jsError("Only I2C1 supported"); return; } - Pin scl = info->pinSCL !=PIN_UNDEFINED ? info->pinSCL : 14; - Pin sda = info->pinSDA !=PIN_UNDEFINED ? info->pinSDA : 2; + Pin scl = info->pinSCL != PIN_UNDEFINED ? info->pinSCL : 12; + Pin sda = info->pinSDA != PIN_UNDEFINED ? info->pinSDA : 13; jshPinSetState(scl, JSHPINSTATE_I2C); jshPinSetState(sda, JSHPINSTATE_I2C); @@ -1150,12 +1151,12 @@ unsigned int jshGetRandomNumber() { /** * Determine available flash depending on EEprom size * - */ + */ uint32_t jshFlashMax() { - extern uint16_t espFlashKB; + extern uint16_t espFlashKB; return 1024*espFlashKB; } - + /** * Read data from flash memory into the buffer. * diff --git a/targets/esp8266/user_main.c b/targets/esp8266/user_main.c index 7043bdea0..e9d30c41e 100644 --- a/targets/esp8266/user_main.c +++ b/targets/esp8266/user_main.c @@ -288,9 +288,34 @@ void user_uart_init() { */ void user_rf_pre_init() { system_update_cpu_freq(160); +// RF calibration: 0=do what byte 114 of esp_init_data_default says, 1=calibrate VDD33 and TX + // power (18ms); 2=calibrate VDD33 only (2ms); 3=full calibration (200ms). The default value of + // byte 114 is 0, which has the same effect as option 2 here. We're using option 3 'cause it's + // unlikely anyone will notice the 200ms or the extra power consumption given that Espruino + // doesn't really support low power sleep modes. + // See the appending of the 2A-ESP8266_IOT_SDK_User_Manual.pdf + system_phy_set_powerup_option(3); // 3: full RF calibration on reset (200ms) + system_phy_set_max_tpw(82); // 82: max TX power //os_printf("Time sys=%u rtc=%u\n", system_get_time(), system_get_rtc_time()); } +/** + * user_rf_cal_sector_set is a required function that is called by the SDK to get a flash + * sector number where it can store RF calibration data. This was introduced with SDK 1.5.4.1 + * and is necessary because Espressif ran out of pre-reserved flash sectors. Ooops... + */ +uint32 +user_rf_cal_sector_set(void) { + uint32_t sect = 0; + switch (system_get_flash_size_map()) { + case FLASH_SIZE_4M_MAP_256_256: // 512KB + sect = 128 - 10; // 0x76000 + default: + sect = 128; // 0x80000 + } + return sect; +} + /** * The main entry point in an ESP8266 application. * It is where the logic of ESP8266 starts. diff --git a/targets/mbed/jshardware.cpp b/targets/mbed/jshardware.cpp deleted file mode 100644 index 28b36b2ce..000000000 --- a/targets/mbed/jshardware.cpp +++ /dev/null @@ -1,285 +0,0 @@ -/* - * This file is part of Espruino, a JavaScript interpreter for Microcontrollers - * - * Copyright (C) 2013 Gordon Williams - * - * This Source Code Form is subject to the terms of the Mozilla Public - * License, v. 2.0. If a copy of the MPL was not distributed with this - * file, You can obtain one at http://mozilla.org/MPL/2.0/. - * - * ---------------------------------------------------------------------------- - * Platform Specific part of Hardware interface Layer - * ---------------------------------------------------------------------------- - */ - #include - #include - #include - -#define CPLUSPLUS -extern "C" { -#include "jshardware.h" -#include "jsutils.h" -#include "jsparse.h" -#include "jsinteractive.h" -} - -#define MBED_PINS (32*5) - -// --------------------------------------------------- MBED DEFS -#include "mbed.h" - -Timer systemTime; -unsigned int systemTimeHigh; -bool systemTimeWasHigh; - -serial_t mbedSerial[USART_COUNT]; -gpio_t mbedPins[MBED_PINS]; -extern "C" { - -// --------------------------------------------------- -void mbedSerialIRQ(uint32_t id, SerialIrq event) { - IOEventFlags device = EV_SERIAL1; // TODO: device - - if (event == RxIrq) { - if (serial_readable(&mbedSerial[id])) - jshPushIOCharEvent(device, (char)serial_getc(&mbedSerial[id])); - } - if (event == TxIrq) { - int c = jshGetCharToTransmit(device); - if (c >= 0) { - serial_putc(&mbedSerial[id], c); - } else - serial_irq_set(&mbedSerial[id], TxIrq, 0); - } -} - - - -// ---------------------------------------------------------------------------- -// for non-blocking IO -void jshInit() { - jshInitDevices(); - systemTimeWasHigh = false; - systemTimeHigh = 0; - systemTime.start(); - int i; - for (i=0;i0) - jshPushIOCharEvent(EV_SERIAL1, serial_getc(&mbedSerial[0])); -} - -// ---------------------------------------------------------------------------- - -int jshGetSerialNumber(unsigned char *data, int maxChars) { - const char *code = "HelloWorld12"; - strncpy((char *)data, code, maxChars); - return strlen(code); -} - -// ---------------------------------------------------------------------------- - -void jshInterruptOff() { -} - -void jshInterruptOn() { -} - -void jshDelayMicroseconds(int microsec) { - wait_us(microsec); -} - -void jshPinSetState(Pin pin, JshPinState state) { - -} - -void jshPinSetValue(Pin pin, bool value) { - gpio_dir(&mbedPins[pin], PIN_OUTPUT); - gpio_write(&mbedPins[pin], value); -} - -bool jshPinGetValue(Pin pin) { - gpio_dir(&mbedPins[pin], PIN_INPUT); - return gpio_read(&mbedPins[pin]); -} - -bool jshIsPinValid(Pin pin) { - return pin>=0 && pin>31; - if (high != systemTimeWasHigh) { - if (!high) systemTimeHigh++; - systemTimeWasHigh = high; - } */ - // FIXME - time after 30 minutes! - - return ((JsSysTime)t);// + ((JsSysTime)systemTimeHigh)<<32; -} - -void jshSetSystemTime(JsSysTime time) { -} - -// ---------------------------------------------------------------------------- - -JsVarFloat jshPinAnalog(Pin pin) { - JsVarFloat value = 0; - return value; -} - -JshPinFunction jshPinAnalogOutput(Pin pin, JsVarFloat value, JsVarFloat freq, JshAnalogOutputFlags flags) { // if freq<=0, the default is used - return JSH_NOTHING; -} - -void jshPinPulse(Pin pin, bool value, JsVarFloat time) { -} - -IOEventFlags jshPinWatch(Pin pin, bool shouldWatch) { - return EV_NONE; -} - -bool jshGetWatchedPinState(IOEventFlags device) { - return false; -} - -bool jshIsEventForPin(IOEvent *event, Pin pin) { - return false; -} - -void jshUSARTSetup(IOEventFlags device, JshUSARTInfo *inf) { -} - -/** Kick a device into action (if required). For instance we may need - * to set up interrupts */ -void jshUSARTKick(IOEventFlags device) { - int id = 0; // TODO: device - int c = jshGetCharToTransmit(device); - if (c >= 0) { - serial_irq_set(&mbedSerial[id], TxIrq, 1); - serial_putc(&mbedSerial[id], c); - } -} - -void jshSPISetup(IOEventFlags device, JshSPIInfo *inf) { -} - -/** Send data through the given SPI device (if data>=0), and return the result - * of the previous send (or -1). If data<0, no data is sent and the function - * waits for data to be returned */ -int jshSPISend(IOEventFlags device, int data) { -} - -/** Send 16 bit data through the given SPI device. */ -void jshSPISend16(IOEventFlags device, int data) { - jshSPISend(device, data>>8); - jshSPISend(device, data&255); -} - -/** Set whether to send 16 bits or 8 over SPI */ -void jshSPISet16(IOEventFlags device, bool is16) { -} - -/** Set whether to use the receive interrupt or not */ -void jshSPISetReceive(IOEventFlags device, bool isReceive) { -} - -void jshI2CSetup(IOEventFlags device, JshI2CInfo *inf) { -} - -void jshI2CWrite(IOEventFlags device, unsigned char address, int nBytes, const unsigned char *data, bool sendStop) { -} - -void jshI2CRead(IOEventFlags device, unsigned char address, int nBytes, unsigned char *data, bool sendStop) { -} - -/// Enter simple sleep mode (can be woken up by interrupts). Returns true on success -bool jshSleep(JsSysTime timeUntilWake) { - __WFI(); // Wait for Interrupt - return true; -} - -void jshUtilTimerDisable() { -} - -void jshUtilTimerReschedule(JsSysTime period) { -} - -void jshUtilTimerStart(JsSysTime period) { -} - -void jshEnableWatchDog(JsVarFloat timeout) { -} - -void jshKickWatchDog() { -} - -JsVarFloat jshReadTemperature() { return NAN; }; -JsVarFloat jshReadVRef() { return NAN; }; -unsigned int jshGetRandomNumber() { return rand(); } - -bool jshFlashGetPage(uint32_t addr, uint32_t *startAddr, uint32_t *pageSize) { - return false; -} - -JsVar *jshFlashGetFree() { - // not implemented, or no free pages. - return 0; -} - -void jshFlashErasePage(uint32_t addr) { -} - -void jshFlashRead(void *buf, uint32_t addr, uint32_t len) { -} - -void jshFlashWrite(void *buf, uint32_t addr, uint32_t len) { -} - -unsigned int jshSetSystemClock(JsVar *options) { - return 0; -} - -// ---------------------------------------------------------------------------- -} // extern C diff --git a/targets/mbed/main.c b/targets/mbed/main.c deleted file mode 100644 index d18fbc075..000000000 --- a/targets/mbed/main.c +++ /dev/null @@ -1,17 +0,0 @@ -#include "platform_config.h" -#include "jsinteractive.h" -#include "jshardware.h" - -// error handler for pure virtual calls -void __cxa_pure_virtual() { while (1); } - -int main() { - jshInit(); - jsvInit(); - jsiInit(true); - - while (1) - jsiLoop(); - - // js*Kill() -} diff --git a/targets/nrf5x/jshardware.c b/targets/nrf5x/jshardware.c index 29eab0dc9..c105e48be 100644 --- a/targets/nrf5x/jshardware.c +++ b/targets/nrf5x/jshardware.c @@ -28,12 +28,13 @@ #ifdef BLUETOOTH #include "jswrap_bluetooth.h" #include "app_timer.h" +#else +#include "nrf_temp.h" #endif #include "nrf_peripherals.h" #include "nrf_gpio.h" #include "nrf_gpiote.h" -#include "nrf_temp.h" #include "nrf_timer.h" #include "nrf_delay.h" #ifdef NRF52 @@ -57,7 +58,7 @@ /* S110_SoftDevice_Specification_2.0.pdf - RTC0 not usable + RTC0 not usable (SoftDevice) RTC1 used by app_timer.c TIMER0 (32 bit) not usable (softdevice) TIMER1 (16 bit on nRF51, 32 bit on nRF52) used by jshardware util timer @@ -271,15 +272,25 @@ bool jshIsUSBSERIALConnected() { return true; } +/// Hack because we *really* don't want to mess with RTC0 :) +JsSysTime baseSystemTime = 0; +uint32_t lastSystemTime = 0; + /// Get the system time (in ticks) JsSysTime jshGetSystemTime() { + // Detect RTC overflows + uint32_t systemTime = NRF_RTC0->COUNTER; + if (lastSystemTime > systemTime) + baseSystemTime += 0x1000000; // it's a 24 bit counter + lastSystemTime = systemTime; // Use RTC0 (also used by BLE stack) - as app_timer starts/stops RTC1 - return (JsSysTime)NRF_RTC0->COUNTER; + return baseSystemTime + (JsSysTime)systemTime; } /// Set the system time (in ticks) - this should only be called rarely as it could mess up things like jsinteractive's timers! void jshSetSystemTime(JsSysTime time) { - + baseSystemTime = 0; + baseSystemTime = time - jshGetSystemTime(); } /// Convert a time in Milliseconds to one in ticks. @@ -332,18 +343,30 @@ void jshPinSetState(Pin pin, JshPinState state) { case JSHPINSTATE_UNDEFINED : nrf_gpio_cfg_default(ipin); break; + case JSHPINSTATE_AF_OUT : case JSHPINSTATE_GPIO_OUT : + case JSHPINSTATE_USART_OUT : nrf_gpio_cfg_output(ipin); break; + case JSHPINSTATE_AF_OUT_OPENDRAIN : case JSHPINSTATE_GPIO_OUT_OPENDRAIN : NRF_GPIO->PIN_CNF[ipin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + break; + case JSHPINSTATE_I2C : + case JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP: + NRF_GPIO->PIN_CNF[ipin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); break; case JSHPINSTATE_GPIO_IN : case JSHPINSTATE_ADC_IN : + case JSHPINSTATE_USART_IN : nrf_gpio_cfg_input(ipin, NRF_GPIO_PIN_NOPULL); break; case JSHPINSTATE_GPIO_IN_PULLUP : @@ -352,25 +375,7 @@ void jshPinSetState(Pin pin, JshPinState state) { case JSHPINSTATE_GPIO_IN_PULLDOWN : nrf_gpio_cfg_input(ipin, NRF_GPIO_PIN_PULLDOWN); break; - /*case JSHPINSTATE_AF_OUT : - break; - case JSHPINSTATE_AF_OUT_OPENDRAIN : - break; - case JSHPINSTATE_USART_IN : - break; - case JSHPINSTATE_USART_OUT : - break; - case JSHPINSTATE_DAC_OUT : - break;*/ - case JSHPINSTATE_I2C : - NRF_GPIO->PIN_CNF[ipin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - // may need to be set to GPIO_PIN_CNF_DIR_Output as well depending on I2C state? - break; - default : assert(0); + default : jsiConsolePrintf("Unimplemented pin state %d\n", state); break; } } @@ -378,7 +383,28 @@ void jshPinSetState(Pin pin, JshPinState state) { /** Get the pin state (only accurate for simple IO - won't return JSHPINSTATE_USART_OUT for instance). * Note that you should use JSHPINSTATE_MASK as other flags may have been added */ JshPinState jshPinGetState(Pin pin) { - return 0; // FIXME need to get able to get pin state! + uint32_t ipin = (uint32_t)pinInfo[pin].pin; + uint32_t p = NRF_GPIO->PIN_CNF[ipin]; + if ((p&GPIO_PIN_CNF_DIR_Msk)==(GPIO_PIN_CNF_DIR_Output<OUT & (1< jshGetTimeFromMilliseconds(240)) + timeUntilWake = jshGetTimeFromMilliseconds(240); if (timeUntilWake < JSSYSTIME_MAX) { #ifdef BLUETOOTH uint32_t ticks = APP_TIMER_TICKS(jshGetMillisecondsFromTime(timeUntilWake), APP_TIMER_PRESCALER); @@ -900,6 +934,7 @@ bool jshSleep(JsSysTime timeUntilWake) { jsiSetSleep(JSI_SLEEP_ASLEEP); sd_app_evt_wait(); // Go to sleep, wait to be woken up jsiSetSleep(JSI_SLEEP_AWAKE); + jshGetSystemTime(); // check for RTC overflows } #ifdef BLUETOOTH // we don't care about the return codes... @@ -944,9 +979,22 @@ void jshUtilTimerDisable() { // the temperature from the internal temperature sensor JsVarFloat jshReadTemperature() { +#ifdef BLUETOOTH + /* Softdevice makes us fault - we must access + this via the function */ + int32_t temp; + uint32_t err_code = sd_temp_get(&temp); + if (err_code) return NAN; + return temp/4.0; +#else nrf_temp_init(); - - return nrf_temp_read() / 4.0; + NRF_TEMP->TASKS_START = 1; + WAIT_UNTIL(NRF_TEMP->EVENTS_DATARDY != 0, "Temperature"); + NRF_TEMP->EVENTS_DATARDY = 0; + JsVarFloat temp = nrf_temp_read() / 4.0; + NRF_TEMP->TASKS_STOP = 1; + return temp; +#endif } // The voltage that a reading of 1 from `analogRead` actually represents diff --git a/targets/stm32/jshardware.c b/targets/stm32/jshardware.c index fa491efc4..d47973eaa 100644 --- a/targets/stm32/jshardware.c +++ b/targets/stm32/jshardware.c @@ -75,6 +75,11 @@ Pin watchedPins[16]; // Whether a pin is being used for soft PWM or not BITFIELD_DECL(jshPinSoftPWM, JSH_PIN_COUNT); +#ifdef STM32F1 +// F1 can't do opendrain pullup, so we do it manually! +BITFIELD_DECL(jshPinOpendrainPullup, JSH_PIN_COUNT); +#endif + // simple 4 byte buffers for SPI #define JSH_SPIBUF_MASK 3 // 4 bytes volatile unsigned char jshSPIBufHead[SPI_COUNT]; @@ -230,7 +235,7 @@ static ALWAYS_INLINE uint8_t stmPortSource(Pin pin) { #endif*/ } -static ALWAYS_INLINE ADC_TypeDef *stmADC(JsvPinInfoAnalog analog) { +static ADC_TypeDef *stmADC(JsvPinInfoAnalog analog) { if (analog & JSH_ANALOG1) return ADC1; #ifdef ADC2 if (analog & JSH_ANALOG2) return ADC2; @@ -245,7 +250,7 @@ static ALWAYS_INLINE ADC_TypeDef *stmADC(JsvPinInfoAnalog analog) { return ADC1; } -static ALWAYS_INLINE uint8_t stmADCChannel(JsvPinInfoAnalog analog) { +static uint8_t stmADCChannel(JsvPinInfoAnalog analog) { switch (analog & JSH_MASK_ANALOG_CH) { #ifndef STM32F3XX case JSH_ANALOG_CH0 : return ADC_Channel_0; @@ -272,7 +277,7 @@ static ALWAYS_INLINE uint8_t stmADCChannel(JsvPinInfoAnalog analog) { } #ifdef STM32API2 -static ALWAYS_INLINE uint8_t functionToAF(JshPinFunction func) { +static uint8_t functionToAF(JshPinFunction func) { #if defined(STM32F401xx) || defined(STM32F411xx) assert(JSH_AF0==0 && JSH_AF15==15); // check mapping is right return func & JSH_MASK_AF; @@ -835,13 +840,16 @@ void jshDelayMicroseconds(int microsec) { while (iter--) __NOP(); } -ALWAYS_INLINE void jshPinSetState(Pin pin, JshPinState state) { +void jshPinSetState(Pin pin, JshPinState state) { /* Make sure we kill software PWM if we set the pin state * after we've started it */ if (BITFIELD_GET(jshPinSoftPWM, pin)) { BITFIELD_SET(jshPinSoftPWM, pin, 0); jstPinPWM(0,0,pin); } +#ifdef STM32F1 + BITFIELD_SET(jshPinOpendrainPullup, pin, state==JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP); +#endif GPIO_InitTypeDef GPIO_InitStructure; bool out = JSHPINSTATE_IS_OUTPUT(state); @@ -901,14 +909,17 @@ JshPinState jshPinGetState(Pin pin) { } #else int mode = (port->MODER >> (pinNumber*2)) & 3; + int pupd = (port->PUPDR >> (pinNumber*2)) & 3; if (mode==0) { // input - int pupd = (port->PUPDR >> (pinNumber*2)) & 3; if (pupd==1) return JSHPINSTATE_GPIO_IN_PULLUP; if (pupd==2) return JSHPINSTATE_GPIO_IN_PULLDOWN; return JSHPINSTATE_GPIO_IN; } else if (mode==1) { // output - return ((port->OTYPER&pinn) ? JSHPINSTATE_GPIO_OUT_OPENDRAIN : JSHPINSTATE_GPIO_OUT) | - (isOn ? JSHPINSTATE_PIN_IS_ON : 0); + JshPinState on = isOn ? JSHPINSTATE_PIN_IS_ON : 0; + if (port->OTYPER&pinn) { + return ((pupd==1) ? JSHPINSTATE_GPIO_OUT_OPENDRAIN_PULLUP : JSHPINSTATE_GPIO_OUT_OPENDRAIN) | on; + } else + return JSHPINSTATE_GPIO_OUT | on; } else if (mode==2) { // AF return (port->OTYPER&pinn) ? JSHPINSTATE_AF_OUT_OPENDRAIN : JSHPINSTATE_AF_OUT; } else { // 3, analog @@ -962,7 +973,7 @@ static NO_INLINE void jshPinSetFunction(Pin pin, JshPinFunction func) { #endif } -ALWAYS_INLINE void jshPinSetValue(Pin pin, bool value) { +void jshPinSetValue(Pin pin, bool value) { #ifdef STM32API2 if (value) GPIO_SetBits(stmPort(pin), stmPin(pin)); @@ -974,9 +985,23 @@ ALWAYS_INLINE void jshPinSetValue(Pin pin, bool value) { else stmPort(pin)->BRR = stmPin(pin); #endif +#ifdef STM32F1 + // hack for opendrain_pullup mode on F1 + if (BITFIELD_GET(jshPinOpendrainPullup, pin)) { + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = stmPin(pin); + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + if (value) { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + } else { + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + } + GPIO_Init(stmPort(pin), &GPIO_InitStructure); + } +#endif } -ALWAYS_INLINE bool jshPinGetValue(Pin pin) { +bool jshPinGetValue(Pin pin) { return GPIO_ReadInputDataBit(stmPort(pin), stmPin(pin)) != 0; } @@ -1028,6 +1053,9 @@ void jshInit() { for (i=0;i<16;i++) watchedPins[i] = PIN_UNDEFINED; BITFIELD_CLEAR(jshPinSoftPWM); +#ifdef STM32F1 + BITFIELD_CLEAR(jshPinOpendrainPullup); +#endif // enable clocks #if defined(STM32F3) diff --git a/tests/test_arrow_functions.js b/tests/test_arrow_functions.js new file mode 100644 index 000000000..9f47a78db --- /dev/null +++ b/tests/test_arrow_functions.js @@ -0,0 +1,24 @@ +// right now, not all of arrow functions are supported +// no destructuring/other ES6 stuff that isn't supported elsewhere + +var pass = 0; +var tests = 0; + +function t(a,b) { + tests++; + var r = a(1,2,3); + if (r==b) pass++; + else console.log(r,"!=",b); +} + +t( (a)=>{return a*42;}, 42); +t( (a,b)=>{return a+b;}, 1+2); +t( (a,b,c)=>{return a+b+c;}, 1+2+3); + +t( a=>42, 42); +t( ()=>42, 42); +t( (a)=>a*42, 42); +t( (a,b)=>a+b, 1+2); +t( (a,b,c)=>a+b+c, 1+2+3); + +result = pass==tests; diff --git a/tests/test_promise.js b/tests/test_promise.js index 0041ebd4c..4f85db135 100644 --- a/tests/test_promise.js +++ b/tests/test_promise.js @@ -12,7 +12,7 @@ var p = new Promise(function(res,rej) { }).catch(function(r) { if (r=="Hello") passes.push("SimpleReject"); }).then(function(r) { - passes.push("FAIL"); + passes.push("SimpleReject2"); }); var p = new Promise(function(res,rej) { @@ -20,7 +20,7 @@ var p = new Promise(function(res,rej) { }).then(function(r) { if (r=="Hello") passes.push("InstantResolve"); }).catch(function(r) { - passes.push("FAIL"); + passes.push("FAIL1"); }); var p = new Promise(function(res,rej) { @@ -35,13 +35,13 @@ var p = new Promise(function(res,rej) { var p = Promise.resolve("Hello").then(function(r) { if (r=="Hello") passes.push("PreResolved"); }).catch(function(r) { - passes.push("FAIL"); + passes.push("FAIL2"); }); var p = Promise.reject("Hello").catch(function(r) { if (r=="Hello") passes.push("PreRejected"); }).then(function(r) { - passes.push("FAIL"); + passes.push("PreRejected2"); }); @@ -58,12 +58,12 @@ var p = Promise.all([new Promise(function(res,rej) { }), new Promise(function(res,rej) { setTimeout(rej, 10, "Ok"); })]).then(function(r) { - passes.push("FAIL"); + passes.push("FAIL5"); }).catch(function(r) { if (r=="Ok") passes.push("RejectAll"); }); setTimeout(function() { - result = passes == "SimpleReject,InstantResolve,PreResolved,PreRejected,SimpleResolve,Resolve1,Resolve2,ResolveAll,RejectAll"; + result = passes == "SimpleReject,InstantResolve,PreResolved,PreRejected,SimpleReject2,PreRejected2,SimpleResolve,Resolve1,ResolveAll,RejectAll"; if (!result) console.log(""+passes); },30); diff --git a/tests/test_promise2.js b/tests/test_promise2.js new file mode 100644 index 000000000..1aba10c93 --- /dev/null +++ b/tests/test_promise2.js @@ -0,0 +1,19 @@ +var sequence = ""; + +var p = new Promise( function(resolve) { resolve(1); }); +p.then( function(value) { + sequence+="A"+value; + return value + 1; +}).then( function(value) { + sequence+="C"+value; + return new Promise( function( resolve ) { resolve( 4 ); } ); +}).then( function( value ) { + sequence+="D"+value; +} ); +p.then(function(value) { + sequence+="B"+value; +}); +setTimeout(function() { + result = sequence == "A1B1C2D4"; + console.log(result, sequence); +},10); diff --git a/tests/test_promise3.js b/tests/test_promise3.js new file mode 100644 index 000000000..271f5bbbd --- /dev/null +++ b/tests/test_promise3.js @@ -0,0 +1,20 @@ +// https://github.com/espruino/Espruino/issues/894 +// test chaining with catch... +var sequence = ""; + +var p = new Promise( function(resolve,reject) { reject(1); }); +p.catch( function(value) { + sequence+="A"+value; + return value + 1; +}).then( function(value) { + sequence+="C"+value; + return new Promise( function( resolve ) { resolve( 4 ); } ); +}).then( function( value ) { + sequence+="D"+value; +} ); +p.then(function(value) { // 1 +}); +setTimeout(function() { + result = sequence == "A1C2D4"; + console.log(result, sequence); +},10); diff --git a/tests/test_promise4.js b/tests/test_promise4.js new file mode 100644 index 000000000..d9a496263 --- /dev/null +++ b/tests/test_promise4.js @@ -0,0 +1,21 @@ +// https://github.com/espruino/Espruino/issues/894 +// test chaining with catch... +var sequence = ""; + +var p = new Promise( function(resolve,reject) { reject(1); }); +p.then( function(value) { + sequence+="A"+value; + return value + 1; +}).then( function(value) { + sequence+="C"+value; + return new Promise( function( resolve ) { resolve( 4 ); } ); +}).catch( function( value ) { + sequence+="D"+value; +} ); +p.then(function(value) { + sequence+="B"+value; +}); +setTimeout(function() { + result = sequence == "D1"; + console.log(result, sequence); +},10); diff --git a/tests/test_promise5.js b/tests/test_promise5.js new file mode 100644 index 000000000..61cc8b281 --- /dev/null +++ b/tests/test_promise5.js @@ -0,0 +1,21 @@ +// https://github.com/espruino/Espruino/issues/894 +// test chaining with catch... +var sequence = ""; + +var p = new Promise( function(resolve,reject) { resolve(1); }); +p.then( function(value) { + sequence+="A"+value; + return value + 1; +}).catch( function(value) { + sequence+="C"+value; + return new Promise( function( resolve ) { resolve( 4 ); } ); +}).then( function( value ) { + sequence+="D"+value; +} ); +p.then(function(value) { + sequence+="B"+value; +}); +setTimeout(function() { + result = sequence == "A1B1D2"; + console.log(result, sequence); +},10); diff --git a/tests/test_template_literals.js b/tests/test_template_literals.js new file mode 100644 index 000000000..98d35ccbb --- /dev/null +++ b/tests/test_template_literals.js @@ -0,0 +1,18 @@ +var pass = 0; +var tests = 0; + +function cmp(a,b) { + tests++; + if (a==b) return pass++; + console.log(JSON.stringify(a),"!=",JSON.stringify(b)); + return 0; +} +var w = "world"; + +cmp(`Hello`,"Hello"); +cmp(`He$lo`,"He$lo"); +cmp(`Hell${0} world`,"Hell0 world"); +cmp(`H${1+2}ll${0} ${w}`,"H3ll0 world"); +cmp(`Its an ${{}}`,"Its an [object Object]"); + +result = pass==tests;