From d49dfd39566a48266d498b0c24d50fe935da0479 Mon Sep 17 00:00:00 2001
From: Ruben Ayrapetyan <r.ayrapetyan@samsung.com>
Date: Tue, 14 Oct 2014 15:04:17 +0400
Subject: [PATCH] Implementing __aeabi_llsl (ARM Runtime ABI: long long left
 shift).

---
 src/libruntime/target/stm32f4/abi.S | 55 +++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 src/libruntime/target/stm32f4/abi.S

diff --git a/src/libruntime/target/stm32f4/abi.S b/src/libruntime/target/stm32f4/abi.S
new file mode 100644
index 000000000..20be117d8
--- /dev/null
+++ b/src/libruntime/target/stm32f4/abi.S
@@ -0,0 +1,55 @@
+/**
+ * Runtime ABI for ARM architecture
+ */
+
+/**
+ * long long __aeabi_llsl(long long {r1, r0}, int {r2})
+ */
+.thumb_func
+.global __aeabi_llsl
+__aeabi_llsl:
+  // if (r2 >= 64) goto 2f;
+  cmp r2, #64
+  bhs 2f
+
+  // if (r2 < 32) goto 1f;
+  cmp r2, #32
+  blo 1f
+
+  // r1 = (r0 << (r2 - 32));
+  // r0 = 0;
+  sub r2, #32
+  mov r1, r0
+  lsl r1, r2
+  mov r0, #0
+
+  bx lr
+  
+  1:
+  // r1 <<= r2;
+  lsl r1, r2
+
+  // r2 = 32 - r2;
+  rsb r2, r2, #32
+
+  // r1 |= (r0 >> r2);
+  mov r3, r0
+  lsr r3, r2
+  orr r1, r3
+
+  // r2 = 32 - r2;
+  rsb r2, r2, #32
+
+  // r0 <<= r2;
+  lsl r0, r2
+
+  bx lr
+
+  2:
+  // r1 = 0;
+  // r0 = 0;
+  mov r1, #0
+  mov r0, #0
+
+  bx lr
+.end __aeabi_llsl