mirror of
https://github.com/ish-app/ish.git
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220745b6ae
pmuludq, punpckldq, movd, psrlq, psllq, paddq, pand, pxor Fixes libcrypto when the SSE bit is on in cpuid
270 lines
8.1 KiB
C
270 lines
8.1 KiB
C
#include <math.h>
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#include <string.h>
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#include "emu/vec.h"
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#include "emu/cpu.h"
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static inline void zero_xmm(union xmm_reg *xmm) {
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xmm->qw[0] = 0;
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xmm->qw[1] = 0;
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}
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#define VEC_ZERO_COPY(zero, copy) \
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void vec_zero##zero##_copy##copy(NO_CPU, const void *src, void *dst) { \
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memset(dst, 0, zero/8); \
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memcpy(dst, src, copy/8); \
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}
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VEC_ZERO_COPY(128, 128)
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VEC_ZERO_COPY(128, 64)
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VEC_ZERO_COPY(128, 32)
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VEC_ZERO_COPY(64, 64)
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VEC_ZERO_COPY(64, 32)
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VEC_ZERO_COPY(32, 32)
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void vec_merge32(NO_CPU, const void *src, void *dst) {
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memcpy(dst, src, 4);
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}
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void vec_merge64(NO_CPU, const void *src, void *dst) {
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memcpy(dst, src, 8);
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}
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void vec_merge128(NO_CPU, const void *src, void *dst) {
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memcpy(dst, src, 16);
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}
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void vec_imm_shiftl_q128(NO_CPU, const uint8_t amount, union xmm_reg *dst) {
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if (amount > 63) {
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zero_xmm(dst);
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} else {
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dst->qw[0] <<= amount;
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dst->qw[1] <<= amount;
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}
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}
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void vec_imm_shiftl_q64(NO_CPU, const uint8_t amount, union mm_reg *dst) {
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if (amount > 63)
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dst->qw = 0;
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else
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dst->qw <<= amount;
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}
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void vec_imm_shiftr_q128(NO_CPU, const uint8_t amount, union xmm_reg *dst) {
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if (amount > 63) {
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zero_xmm(dst);
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} else {
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dst->qw[0] >>= amount;
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dst->qw[1] >>= amount;
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}
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}
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void vec_imm_shiftr_q64(NO_CPU, const uint8_t amount, union mm_reg *dst) {
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if (amount > 63)
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dst->qw = 0;
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else
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dst->qw >>= amount;
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}
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void vec_shiftl_q128(NO_CPU, union xmm_reg *amount, union xmm_reg *dst) {
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uint64_t amount_qw = amount->qw[0];
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if (amount_qw > 63) {
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zero_xmm(dst);
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} else {
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dst->qw[0] <<= amount_qw;
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dst->qw[1] <<= amount_qw;
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}
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}
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void vec_shiftr_q128(NO_CPU, union xmm_reg *amount, union xmm_reg *dst) {
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uint64_t amount_qw = amount->qw[0];
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if (amount_qw > 63) {
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zero_xmm(dst);
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} else {
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dst->qw[0] >>= amount_qw;
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dst->qw[1] >>= amount_qw;
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}
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}
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void vec_add_b128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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for (unsigned i = 0; i < array_size(src->u8); i++)
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dst->u8[i] += src->u8[i];
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}
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void vec_add_q128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] += src->qw[0];
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dst->qw[1] += src->qw[1];
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}
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void vec_add_q64(NO_CPU, union mm_reg *src, union mm_reg *dst) {
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dst->qw += src->qw;
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}
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void vec_sub_q128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] -= src->qw[0];
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dst->qw[1] -= src->qw[1];
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}
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void vec_mulu_dq128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] = (uint64_t) src->u32[0] * dst->u32[0];
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dst->qw[1] = (uint64_t) src->u32[2] * dst->u32[2];
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}
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void vec_mulu_dq64(NO_CPU, union mm_reg *src, union mm_reg *dst) {
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dst->qw = (uint64_t) src->dw[0] * dst->dw[0];
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}
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void vec_and128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] &= src->qw[0];
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dst->qw[1] &= src->qw[1];
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}
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void vec_and64(NO_CPU, union mm_reg *src, union mm_reg *dst) {
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dst->qw &= src->qw;
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}
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void vec_andn128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] = ~dst->qw[0] & src->qw[0];
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dst->qw[1] = ~dst->qw[1] & src->qw[1];
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}
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void vec_or128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] |= src->qw[0];
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dst->qw[1] |= src->qw[1];
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}
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void vec_xor128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[0] ^= src->qw[0];
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dst->qw[1] ^= src->qw[1];
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}
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void vec_xor64(NO_CPU, union mm_reg *src, union mm_reg *dst) {
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dst->qw ^= src->qw;
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}
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void vec_min_ub128(NO_CPU, union xmm_reg *src, union xmm_reg *dst) {
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for (unsigned i = 0; i < array_size(src->u8); i++)
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if (src->u8[i] < dst->u8[i])
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dst->u8[i] = src->u8[i];
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}
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static bool cmpd(double a, double b, int type) {
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bool res;
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switch (type % 4) {
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case 0: res = a == b; break;
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case 1: res = a < b; break;
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case 2: res = a <= b; break;
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case 3: res = isnan(a) || isnan(b); break;
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}
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if (type >= 4) res = !res;
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return res;
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}
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void vec_single_fcmp64(NO_CPU, const double *src, union xmm_reg *dst, uint8_t type) {
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dst->qw[0] = cmpd(dst->f64[0], *src, type) ? -1 : 0;
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}
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void vec_single_fadd64(NO_CPU, const double *src, double *dst) { *dst += *src; }
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void vec_single_fadd32(NO_CPU, const float *src, float *dst) { *dst += *src; }
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void vec_single_fmul64(NO_CPU, const double *src, double *dst) { *dst *= *src; }
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void vec_single_fmul32(NO_CPU, const float *src, float *dst) { *dst *= *src; }
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void vec_single_fsub64(NO_CPU, const double *src, double *dst) { *dst -= *src; }
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void vec_single_fsub32(NO_CPU, const float *src, float *dst) { *dst -= *src; }
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void vec_single_fdiv64(NO_CPU, const double *src, double *dst) { *dst /= *src; }
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void vec_single_fdiv32(NO_CPU, const float *src, float *dst) { *dst /= *src; }
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void vec_single_fmax64(NO_CPU, const double *src, double *dst) {
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if (*src > *dst || isnan(*src) || isnan(*dst)) *dst = *src;
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}
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void vec_single_fmin64(NO_CPU, const double *src, double *dst) {
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if (*src < *dst || isnan(*src) || isnan(*dst)) *dst = *src;
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}
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void vec_single_ucomi32(struct cpu_state *cpu, const float *src, const float *dst) {
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cpu->zf_res = cpu->pf_res = 0;
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cpu->zf = *src == *dst;
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cpu->cf = *src > *dst;
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cpu->pf = 0;
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if (isnan(*src) || isnan(*dst))
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cpu->zf = cpu->cf = cpu->pf = 1;
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cpu->of = cpu->sf = cpu->af = 0;
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cpu->sf_res = 0;
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}
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void vec_single_ucomi64(struct cpu_state *cpu, const double *src, const double *dst) {
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cpu->zf_res = cpu->pf_res = 0;
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cpu->zf = *src == *dst;
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cpu->cf = *src > *dst;
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cpu->pf = 0;
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if (isnan(*src) || isnan(*dst))
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cpu->zf = cpu->cf = cpu->pf = 1;
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cpu->of = cpu->sf = cpu->af = 0;
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cpu->sf_res = 0;
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}
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// come to the dark side of macros
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#define _ISNAN_int32_t(x) false
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#define _ISNAN_float(x) isnan(x)
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#define _ISNAN_double(x) isnan(x)
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#define _ISNAN(x, t) _ISNAN_##t(x)
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#define VEC_CVT(name, src_t, dst_t) \
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void vec_cvt##name(NO_CPU, const src_t *src, dst_t *dst) { \
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if (_ISNAN(*src, src_t)) \
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*dst = INT32_MIN; \
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else \
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*dst = *src; \
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}
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VEC_CVT(si2sd32, int32_t, double)
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VEC_CVT(tsd2si64, double, int32_t)
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VEC_CVT(sd2ss64, double, float)
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VEC_CVT(si2ss32, int32_t, float)
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VEC_CVT(tss2si32, float, int32_t)
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VEC_CVT(ss2sd32, float, double)
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void vec_unpack_bw128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst) {
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for (int i = 7; i >= 0; i--) {
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dst->u8[i*2 + 1] = src->u8[i];
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dst->u8[i*2] = dst->u8[i];
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}
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}
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void vec_unpack_dq128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst) {
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dst->u32[3] = src->u32[1];
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dst->u32[2] = dst->u32[1];
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dst->u32[1] = src->u32[0];
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}
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void vec_unpack_dq64(NO_CPU, const union mm_reg *src, union mm_reg *dst) {
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dst->dw[1] = src->dw[0];
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}
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void vec_unpack_qdq128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst) {
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dst->qw[1] = src->qw[0];
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}
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void vec_shuffle_lw128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst, uint8_t encoding) {
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union xmm_reg src_copy = *src;
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for (int i = 0; i < 4; i++)
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dst->u16[i] = src_copy.u16[(encoding >> (i*2)) % 4];
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dst->qw[1] = src->qw[1];
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}
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void vec_shuffle_d128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst, uint8_t encoding) {
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union xmm_reg src_copy = *src;
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for (int i = 0; i < 4; i++)
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dst->u32[i] = src_copy.u32[(encoding >> (i*2)) % 4];
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}
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void vec_compare_eqb128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst) {
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for (unsigned i = 0; i < array_size(src->u8); i++)
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dst->u8[i] = dst->u8[i] == src->u8[i] ? ~0 : 0;
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}
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void vec_compare_eqd128(NO_CPU, const union xmm_reg *src, union xmm_reg *dst) {
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for (unsigned i = 0; i < array_size(src->u32); i++)
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dst->u32[i] = dst->u32[i] == src->u32[i] ? ~0 : 0;
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}
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void vec_movmask_b128(NO_CPU, const union xmm_reg *src, uint32_t *dst) {
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*dst = 0;
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for (unsigned i = 0; i < array_size(src->u8); i++) {
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if (src->u8[i] & (1 << 7))
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*dst |= 1 << i;
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}
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}
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void vec_fmovmask_d128(NO_CPU, const union xmm_reg *src, uint32_t *dst) {
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*dst = 0;
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for (unsigned i = 0; i < array_size(src->f64); i++) {
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if (signbit(src->f64[i]))
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*dst |= 1 << i;
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}
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}
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void vec_extract_w128(NO_CPU, const union xmm_reg *src, uint32_t *dst, uint8_t index) {
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*dst = src->u16[index % 8];
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}
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