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1595 lines
26 KiB
C
1595 lines
26 KiB
C
/** @file
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Copyright (C) 2021, PMheart. All rights reserved.
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Copyright (C) 2021, vit9696. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Uefi.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciIo.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/OcDeviceMiscLib.h>
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#include <Library/PrintLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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typedef struct PCI_CLASS_ENTRY_TAG {
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UINT8 Code; // Class, subclass or interface code
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CONST CHAR8 *DescText; // Description string
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CONST struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or interface if any
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} PCI_CLASS_ENTRY;
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//
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// PCI subclasses.
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//
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//
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// Pre-classcode subclass.
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//
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STATIC CONST PCI_CLASS_ENTRY mPciClass00PreClassCode[] = {
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{
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PCI_CLASS_OLD_OTHER,
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"Other device",
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NULL
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},
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{
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PCI_CLASS_OLD_VGA,
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"VGA-compatible device",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Mass storage subclasses.
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//
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// SCSI controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage00[] = {
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{
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0x00,
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"SCSI controller",
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NULL
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},
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{
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0x11,
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"SCSI storage device SOP using PQI",
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NULL
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},
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{
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0x12,
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"SCSI controller SOP using PQI",
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NULL
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},
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{
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0x13,
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"SCSI storage device and controller SOP using PQI",
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NULL
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},
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{
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0x21,
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"SCSI storage device SOP using NVMe",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// ATA controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage05[] = {
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{
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0x20,
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"ATA controller with single stepping ADMA interface",
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NULL
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},
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{
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0x30,
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"ATA controller with continous ADMA interface",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// Serial ATA controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage06[] = {
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{
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0x00,
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"Serial ATA controller",
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NULL
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},
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{
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0x01,
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"Serial ATA controller using AHCI",
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NULL
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},
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{
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0x02,
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"Serial Storage Bus interface",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// Non-volatile memory subsystem interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage08[] = {
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{
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0x00,
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"Non-volatile memory subsystem",
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NULL
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},
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{
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0x01,
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"Non-volatile memory subsystem using NVMHCI",
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NULL
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},
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{
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0x02,
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"NVM Express I/O controller",
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NULL
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},
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{
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0x03,
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"NVM Express administrative controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// Universal Flash Storage controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage09[] = {
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{
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0x00,
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"Universal Flash Storage controller",
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NULL
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},
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{
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0x01,
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"Universal Flash Storage controller using UFSHCI",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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STATIC CONST PCI_CLASS_ENTRY mPciClass01MassStorage[] = {
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{
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PCI_CLASS_MASS_STORAGE_SCSI,
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"SCSI controller",
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mPciClass01MassStorage00
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},
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{
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PCI_CLASS_MASS_STORAGE_IDE,
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"IDE controller",
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NULL
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},
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{
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PCI_CLASS_MASS_STORAGE_FLOPPY,
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"Floppy controller",
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NULL
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},
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{
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PCI_CLASS_MASS_STORAGE_IPI,
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"IPI bus controller",
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NULL
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},
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{
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PCI_CLASS_MASS_STORAGE_RAID,
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"RAID controller",
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NULL
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},
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{
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0x05,
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"ATA controller",
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mPciClass01MassStorage05
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},
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{
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0x06,
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"Serial ATA controller",
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mPciClass01MassStorage06
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},
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{
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0x07,
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"Serial Attached SCSI controller",
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NULL
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},
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{
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0x08,
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"Non-volatile memory subsystem",
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mPciClass01MassStorage08
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},
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{
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0x09,
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"Universal Flash Storage controller",
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mPciClass01MassStorage09
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},
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{
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PCI_CLASS_MASS_STORAGE_OTHER,
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"Other mass storage controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Network controller subclasses.
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//
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STATIC CONST PCI_CLASS_ENTRY mPciClass02Network[] = {
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{
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PCI_CLASS_NETWORK_ETHERNET,
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"Ethernet controller",
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NULL
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},
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{
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PCI_CLASS_NETWORK_TOKENRING,
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"Token Ring controller",
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NULL
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},
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{
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PCI_CLASS_NETWORK_FDDI,
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"FDDI controller",
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NULL
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},
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{
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PCI_CLASS_NETWORK_ATM,
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"ATM controller",
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NULL
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},
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{
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PCI_CLASS_NETWORK_ISDN,
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"ISDN controller",
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NULL
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},
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{
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0x05,
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"WorldFip controller",
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NULL
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},
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{
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0x06,
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"PCMIG 2.14 Multi Computing",
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NULL
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},
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{
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0x07,
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"InfiniBand controller",
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NULL
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},
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{
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0x08,
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"Host fabric controller",
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NULL
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},
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{
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PCI_CLASS_NETWORK_OTHER,
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"Other network controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Display controller subclasses.
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//
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// VGA controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass03Display00[] = {
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{
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PCI_IF_VGA_VGA,
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"VGA-compatible controller",
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NULL
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},
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{
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PCI_IF_VGA_8514,
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"8514-compatible controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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STATIC CONST PCI_CLASS_ENTRY mPciClass03Display[] = {
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{
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PCI_CLASS_DISPLAY_VGA,
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"VGA controller",
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mPciClass03Display00
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},
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{
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PCI_CLASS_DISPLAY_XGA,
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"XGA controller",
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NULL
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},
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{
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PCI_CLASS_DISPLAY_3D,
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"3D controller",
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NULL
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},
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{
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PCI_CLASS_DISPLAY_OTHER,
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"Other display controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Multimedia controller subclasses.
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//
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STATIC CONST PCI_CLASS_ENTRY mPciClass04Multimedia[] = {
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{
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PCI_CLASS_MEDIA_VIDEO,
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"Video device",
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NULL
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},
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{
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PCI_CLASS_MEDIA_AUDIO,
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"Audio device",
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NULL
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},
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{
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PCI_CLASS_MEDIA_TELEPHONE,
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"Telephony device",
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NULL
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},
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{
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0x03,
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"High definition audio device",
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NULL
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},
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{
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PCI_CLASS_MEDIA_OTHER,
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"Other multimedia device",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Memory controller subclasses.
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//
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STATIC CONST PCI_CLASS_ENTRY mPciClass05Memory[] = {
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{
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PCI_CLASS_MEMORY_RAM,
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"RAM controller",
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NULL
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},
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{
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PCI_CLASS_MEMORY_FLASH,
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"Flash memory controller",
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NULL
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},
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{
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PCI_CLASS_MEMORY_OTHER,
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"Other memory controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Bridge subclasses.
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//
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STATIC CONST PCI_CLASS_ENTRY mPciClass06Bridge[] = {
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{
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PCI_CLASS_BRIDGE_HOST,
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"Host bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_ISA,
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"ISA bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_EISA,
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"EISA bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_MCA,
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"MCA bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_P2P,
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"PCI-to-PCI bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_PCMCIA,
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"PCMCIA bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_CARDBUS,
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"CardBus bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_RACEWAY,
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"RACEway bridge",
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NULL
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},
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{
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0x09,
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"Semi-transparent PCI-to-PCI bridge",
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NULL
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},
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{
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0x0A,
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"InfiniBand-to-PCI host bridge",
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NULL
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},
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{
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0x0B,
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"Advanced Switching to PCI host bridge",
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NULL
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},
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{
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PCI_CLASS_BRIDGE_OTHER,
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"Other bridge device",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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//
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// Simple communication controller subclasses.
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//
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// Serial controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms00[] = {
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{
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PCI_IF_GENERIC_XT,
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"Generic XT-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16450,
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"16450-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16550,
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"16550-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16650,
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"16650-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16750,
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"16750-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16850,
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"16850-compatible serial controller",
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NULL
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},
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{
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PCI_IF_16950,
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"16950-compatible serial controller",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// Parallel controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms01[] = {
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{
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PCI_IF_PARALLEL_PORT,
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"Parallel port",
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NULL
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},
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{
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PCI_IF_BI_DIR_PARALLEL_PORT,
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"Bi-directional parallel port",
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NULL
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},
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{
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PCI_IF_ECP_PARALLEL_PORT,
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"ECP parallel port",
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NULL
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},
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{
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PCI_IF_1284_CONTROLLER,
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"IEEE1284 controller",
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NULL
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},
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{
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PCI_IF_1284_DEVICE,
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"IEEE1284 device",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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// Modem interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms03[] = {
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{
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PCI_IF_GENERIC_MODEM,
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"Generic modem",
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NULL
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},
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{
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PCI_IF_16450_MODEM,
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"Hayes compatible modem, 16450-compatible interface",
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NULL
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},
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{
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PCI_IF_16550_MODEM,
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"Hayes compatible modem, 16550-compatible interface",
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NULL
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},
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{
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PCI_IF_16650_MODEM,
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"Hayes compatible modem, 16650-compatible interface",
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NULL
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},
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{
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PCI_IF_16750_MODEM,
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"Hayes compatible modem, 16750-compatible interface",
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NULL
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},
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{
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0x00,
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NULL,
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NULL
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}
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};
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STATIC CONST PCI_CLASS_ENTRY mPciClass07SimpleComms[] = {
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{
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PCI_SUBCLASS_SERIAL,
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"Serial controller",
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mPciClass07SimpleComms00
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},
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{
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PCI_SUBCLASS_PARALLEL,
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"Parallel controller",
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mPciClass07SimpleComms01
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},
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{
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PCI_SUBCLASS_MULTIPORT_SERIAL,
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"Multiport serial controller",
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NULL
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},
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{
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PCI_SUBCLASS_MODEM,
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"Modem",
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mPciClass07SimpleComms03
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},
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{
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0x04,
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"GPIB (IEEE448.1/2) controller",
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NULL
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},
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{
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0x05,
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"Smart Card",
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NULL
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},
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{
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PCI_SUBCLASS_SCC_OTHER,
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"Other communications device",
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NULL
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},
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|
{
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0x00,
|
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NULL,
|
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NULL
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}
|
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};
|
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|
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//
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// System peripheral subclasses.
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//
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|
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// Interrupt controller interfaces.
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STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip00[] = {
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{
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PCI_IF_8259_PIC,
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"Generic 8259 programmable interrupt controller",
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NULL
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},
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{
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PCI_IF_ISA_PIC,
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"ISA programmable interrupt controller",
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NULL
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},
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|
{
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PCI_IF_EISA_PIC,
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|
"EISA programmable interrupt controller",
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NULL
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},
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{
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PCI_IF_APIC_CONTROLLER,
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"I/O APIC interrupt controller",
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NULL
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|
},
|
|
{
|
|
PCI_IF_APIC_CONTROLLER2,
|
|
"I/O x2 APIC interrupt controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
// DMA controller interfaces.
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip01[] = {
|
|
{
|
|
PCI_IF_8237_DMA,
|
|
"Generic 8237 DMA controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_ISA_DMA,
|
|
"ISA DMA controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_EISA_DMA,
|
|
"EISA DMA controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
// Timer interfaces.
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip02[] = {
|
|
{
|
|
PCI_IF_8254_TIMER,
|
|
"Generic 8254 system timer",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_ISA_TIMER,
|
|
"ISA system timer",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_EISA_TIMER,
|
|
"EISA system timer",
|
|
NULL
|
|
},
|
|
{
|
|
0x04,
|
|
"High Performance Event Timer",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
// RTC interfaces.
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip03[] = {
|
|
{
|
|
PCI_IF_GENERIC_RTC,
|
|
"Generic RTC controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_ISA_RTC,
|
|
"ISA RTC controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass08SystemPerip[] = {
|
|
{
|
|
PCI_SUBCLASS_PIC,
|
|
"Programmable interrupt controller",
|
|
mPciClass08SystemPerip00
|
|
},
|
|
{
|
|
PCI_SUBCLASS_DMA,
|
|
"DMA controller",
|
|
mPciClass08SystemPerip01
|
|
},
|
|
{
|
|
PCI_SUBCLASS_TIMER,
|
|
"System timer",
|
|
mPciClass08SystemPerip02
|
|
},
|
|
{
|
|
PCI_SUBCLASS_RTC,
|
|
"RTC controller",
|
|
mPciClass08SystemPerip03
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PNP_CONTROLLER,
|
|
"Generic PCI Hot-Plug controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x05,
|
|
"SD Host controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x06,
|
|
"IOMMU",
|
|
NULL
|
|
},
|
|
{
|
|
0x07,
|
|
"Root Complex Event Collector",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PERIPHERAL_OTHER,
|
|
"Other system peripheral",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Input device subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass09Input[] = {
|
|
{
|
|
PCI_SUBCLASS_KEYBOARD,
|
|
"Keyboard controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PEN,
|
|
"Pen controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_MOUSE_CONTROLLER,
|
|
"Mouse controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_SCAN_CONTROLLER,
|
|
"Scanner controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_GAMEPORT,
|
|
"Gameport controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_INPUT_OTHER,
|
|
"Other input controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Docking station subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0ADocking[] = {
|
|
{
|
|
PCI_SUBCLASS_DOCKING_GENERIC,
|
|
"Generic docking station",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_DOCKING_OTHER,
|
|
"Other docking station",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Processor subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0BProcessor[] = {
|
|
{
|
|
PCI_SUBCLASS_PROC_386,
|
|
"386 processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_486,
|
|
"486 processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_PENTIUM,
|
|
"Pentium processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_ALPHA,
|
|
"Alpha processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_POWERPC,
|
|
"PowerPC processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_MIPS,
|
|
"MIPS processor",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_PROC_CO_PORC,
|
|
"Co-processor",
|
|
NULL
|
|
},
|
|
{
|
|
0x80,
|
|
"Other processor",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Serial bus controller subclasses.
|
|
//
|
|
|
|
// FireWire controller interfaces
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus00[] = {
|
|
{
|
|
PCI_IF_1394,
|
|
"IEEE 1394 FireWire controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_1394_OPEN_HCI,
|
|
"IEEE 1394 OHCI controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
// USB controller interfaces
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus03[] = {
|
|
{
|
|
PCI_IF_UHCI,
|
|
"Universal Serial Bus UHCI controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_OHCI,
|
|
"Universal Serial Bus OHCI controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x20,
|
|
"Universal Serial Bus EHCI controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x30,
|
|
"Universal Serial Bus xHCI controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x40,
|
|
"USB4 Host Interface controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_USB_OTHER,
|
|
"Other Universal Serial Bus controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_IF_USB_DEVICE,
|
|
"Universal Serial Bus device",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0CSerialBus[] = {
|
|
{
|
|
PCI_CLASS_SERIAL_FIREWIRE,
|
|
"FireWire controller",
|
|
mPciClass0CSerialBus00
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL_ACCESS_BUS,
|
|
"ACCESS.bus",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL_SSA,
|
|
"SSA",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL_USB,
|
|
"Universal Serial Bus controller",
|
|
mPciClass0CSerialBus03
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL_FIBRECHANNEL,
|
|
"Fibre Channel controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL_SMB,
|
|
"SMBus controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x06,
|
|
"InfiniBand controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x07,
|
|
"IPMI controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x08,
|
|
"SERCOS Interface Standard controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x09,
|
|
"CANbus controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x09,
|
|
"MIPI I3C Host Controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x80,
|
|
"Other serial bus controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Wireless subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0DWireless[] = {
|
|
{
|
|
PCI_SUBCLASS_IRDA,
|
|
"irDA-compatible controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_IR,
|
|
"Consumer IR controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_RF,
|
|
"RF controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x11,
|
|
"Bluetooth controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x12,
|
|
"Broadband controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x20,
|
|
"Ethernet 802.11a controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x21,
|
|
"Ethernet 802.11b controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x40,
|
|
"Cellular controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x41,
|
|
"Cellular controller plus Ethernet 802.11",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_WIRELESS_OTHER,
|
|
"Other wireless controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Satellite communication subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass0FSatellite[] = {
|
|
{
|
|
PCI_SUBCLASS_TV,
|
|
"Satellite TV controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_AUDIO,
|
|
"Satellite audio controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_VOICE,
|
|
"Satellite voice controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_DATA,
|
|
"Satellite data controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x80,
|
|
"Other satellite controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Encryption/decryption subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass10EncryptionDecryption[] = {
|
|
{
|
|
PCI_SUBCLASS_NET_COMPUT,
|
|
"Network and computing encryption and decryption controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_ENTERTAINMENT,
|
|
"Entertainment encryption and decryption controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_SECURITY_OTHER,
|
|
"Other encryption and decryption controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// Data acquisition and signal processing subclasses.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClass11DataAcquisition[] = {
|
|
{
|
|
PCI_SUBCLASS_DPIO,
|
|
"DPIO module",
|
|
NULL
|
|
},
|
|
{
|
|
0x01,
|
|
"Performance counters",
|
|
NULL
|
|
},
|
|
{
|
|
0x10,
|
|
"Communications synchronization plus time and frequency test/measurement",
|
|
NULL
|
|
},
|
|
{
|
|
0x20,
|
|
"Management card",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_SUBCLASS_DPIO_OTHER,
|
|
"Other data acquisition/signal processing controller",
|
|
NULL
|
|
},
|
|
{
|
|
0x00,
|
|
NULL,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
//
|
|
// PCI classes.
|
|
//
|
|
STATIC CONST PCI_CLASS_ENTRY mPciClasses[] = {
|
|
{
|
|
PCI_CLASS_OLD,
|
|
"Legacy PCI class",
|
|
mPciClass00PreClassCode
|
|
},
|
|
{
|
|
PCI_CLASS_MASS_STORAGE,
|
|
"Mass storage controller",
|
|
mPciClass01MassStorage
|
|
},
|
|
{
|
|
PCI_CLASS_NETWORK,
|
|
"Network controller",
|
|
mPciClass02Network
|
|
},
|
|
{
|
|
PCI_CLASS_DISPLAY,
|
|
"Display controller",
|
|
mPciClass03Display
|
|
},
|
|
{
|
|
PCI_CLASS_MEDIA,
|
|
"Multimedia controller",
|
|
mPciClass04Multimedia
|
|
},
|
|
{
|
|
PCI_CLASS_MEMORY_CONTROLLER,
|
|
"Memory controller",
|
|
mPciClass05Memory
|
|
},
|
|
{
|
|
PCI_CLASS_BRIDGE,
|
|
"Bridge device",
|
|
mPciClass06Bridge
|
|
},
|
|
{
|
|
PCI_CLASS_SCC,
|
|
"Simple communications controller",
|
|
mPciClass07SimpleComms
|
|
},
|
|
{
|
|
PCI_CLASS_SYSTEM_PERIPHERAL,
|
|
"Base system peripheral",
|
|
mPciClass08SystemPerip
|
|
},
|
|
{
|
|
PCI_CLASS_INPUT_DEVICE,
|
|
"Input device",
|
|
mPciClass09Input
|
|
},
|
|
{
|
|
PCI_CLASS_DOCKING_STATION,
|
|
"Docking station",
|
|
mPciClass0ADocking
|
|
},
|
|
{
|
|
PCI_CLASS_PROCESSOR,
|
|
"Processor",
|
|
mPciClass0BProcessor
|
|
},
|
|
{
|
|
PCI_CLASS_SERIAL,
|
|
"Serial bus controller",
|
|
mPciClass0CSerialBus
|
|
},
|
|
{
|
|
PCI_CLASS_WIRELESS,
|
|
"Wireless controller",
|
|
mPciClass0DWireless
|
|
},
|
|
{
|
|
PCI_CLASS_INTELLIGENT_IO,
|
|
"Intelligent I/O controller",
|
|
NULL
|
|
},
|
|
{
|
|
PCI_CLASS_SATELLITE,
|
|
"Satellite communication controller",
|
|
mPciClass0FSatellite
|
|
},
|
|
{
|
|
PCI_SECURITY_CONTROLLER,
|
|
"Encryption/decryption controller",
|
|
mPciClass10EncryptionDecryption
|
|
},
|
|
{
|
|
PCI_CLASS_DPIO,
|
|
"Data acquisition and signal processing controller",
|
|
mPciClass11DataAcquisition
|
|
},
|
|
{
|
|
0x12,
|
|
"Processing accelerator",
|
|
NULL
|
|
},
|
|
{
|
|
0x13,
|
|
"Non-essential instrumentation function"
|
|
}
|
|
};
|
|
|
|
STATIC
|
|
VOID
|
|
GetPciDeviceClassText (
|
|
IN UINT8 BaseClass,
|
|
IN UINT8 SubClass,
|
|
IN UINT8 Interface,
|
|
OUT CONST CHAR8 **TextBaseClass,
|
|
OUT CONST CHAR8 **TextSubClass
|
|
)
|
|
{
|
|
UINTN Index;
|
|
CONST PCI_CLASS_ENTRY *BaseClassEntry;
|
|
CONST PCI_CLASS_ENTRY *SubClassEntry;
|
|
CONST PCI_CLASS_ENTRY *InterfaceEntry;
|
|
|
|
//
|
|
// Get base class.
|
|
//
|
|
BaseClassEntry = NULL;
|
|
for (Index = 0; Index < ARRAY_SIZE (mPciClasses); Index++) {
|
|
if (mPciClasses[Index].Code == BaseClass) {
|
|
BaseClassEntry = &mPciClasses[Index];
|
|
}
|
|
}
|
|
|
|
if (BaseClassEntry == NULL) {
|
|
*TextBaseClass = "Unknown class";
|
|
*TextSubClass = NULL;
|
|
return;
|
|
}
|
|
|
|
*TextBaseClass = BaseClassEntry->DescText;
|
|
|
|
//
|
|
// Get subclass if present.
|
|
//
|
|
if (BaseClassEntry->LowerLevelClass == NULL) {
|
|
*TextSubClass = NULL;
|
|
return;
|
|
}
|
|
|
|
Index = 0;
|
|
SubClassEntry = NULL;
|
|
while (BaseClassEntry->LowerLevelClass[Index].DescText != NULL) {
|
|
if (BaseClassEntry->LowerLevelClass[Index].Code == SubClass) {
|
|
SubClassEntry = &BaseClassEntry->LowerLevelClass[Index];
|
|
break;
|
|
}
|
|
|
|
Index++;
|
|
}
|
|
|
|
//
|
|
// Use other subclass if subclass not found.
|
|
//
|
|
if (SubClassEntry == NULL) {
|
|
Index = 0;
|
|
while (BaseClassEntry->LowerLevelClass[Index].DescText != NULL) {
|
|
if (BaseClassEntry->LowerLevelClass[Index].Code == SubClass) {
|
|
SubClassEntry = &BaseClassEntry->LowerLevelClass[Index];
|
|
break;
|
|
}
|
|
|
|
Index++;
|
|
}
|
|
}
|
|
|
|
if (SubClassEntry == NULL) {
|
|
*TextSubClass = NULL;
|
|
return;
|
|
}
|
|
|
|
//
|
|
// Get interface if present.
|
|
//
|
|
if (SubClassEntry->LowerLevelClass == NULL) {
|
|
*TextSubClass = SubClassEntry->DescText;
|
|
return;
|
|
}
|
|
|
|
Index = 0;
|
|
InterfaceEntry = NULL;
|
|
while (SubClassEntry->LowerLevelClass[Index].DescText != NULL) {
|
|
if (SubClassEntry->LowerLevelClass[Index].Code == Interface) {
|
|
InterfaceEntry = &SubClassEntry->LowerLevelClass[Index];
|
|
break;
|
|
}
|
|
|
|
Index++;
|
|
}
|
|
|
|
if (InterfaceEntry == NULL) {
|
|
*TextSubClass = SubClassEntry->DescText;
|
|
return;
|
|
}
|
|
|
|
*TextSubClass = InterfaceEntry->DescText;
|
|
}
|
|
|
|
EFI_STATUS
|
|
OcPciInfoDump (
|
|
IN EFI_FILE_PROTOCOL *Root
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UINTN HandleCount;
|
|
EFI_HANDLE *HandleBuffer;
|
|
UINTN Index;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
PCI_TYPE00 PciDevice;
|
|
CONST CHAR8 *TextPciClass;
|
|
CONST CHAR8 *TextPciSubClass;
|
|
EFI_DEVICE_PATH_PROTOCOL *PciDevicePath;
|
|
CHAR16 *TextPciDevicePath;
|
|
|
|
CHAR8 *FileBuffer;
|
|
UINTN FileBufferSize;
|
|
CHAR16 TmpFileName[32];
|
|
|
|
ASSERT (Root != NULL);
|
|
|
|
FileBufferSize = SIZE_1KB;
|
|
FileBuffer = AllocateZeroPool (FileBufferSize);
|
|
if (FileBuffer == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
Status = gBS->LocateHandleBuffer (
|
|
ByProtocol,
|
|
&gEfiPciIoProtocolGuid,
|
|
NULL,
|
|
&HandleCount,
|
|
&HandleBuffer
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG ((DEBUG_INFO, "OCDM: No PCI devices found for dumping - %r\n", Status));
|
|
FreePool (FileBuffer);
|
|
return Status;
|
|
}
|
|
|
|
for (Index = 0; Index < HandleCount; ++Index) {
|
|
Status = gBS->HandleProtocol (
|
|
HandleBuffer[Index],
|
|
&gEfiPciIoProtocolGuid,
|
|
(VOID **)&PciIo
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// Read the whole PCI device in 32-bit.
|
|
//
|
|
Status = PciIo->Pci.Read (
|
|
PciIo,
|
|
EfiPciIoWidthUint32,
|
|
0,
|
|
sizeof (PCI_TYPE00) / sizeof (UINT32),
|
|
&PciDevice
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// Dump PCI class text.
|
|
//
|
|
GetPciDeviceClassText (
|
|
PciDevice.Hdr.ClassCode[2],
|
|
PciDevice.Hdr.ClassCode[1],
|
|
PciDevice.Hdr.ClassCode[0],
|
|
&TextPciClass,
|
|
&TextPciSubClass
|
|
);
|
|
if (TextPciSubClass != NULL) {
|
|
OcAsciiPrintBuffer (
|
|
&FileBuffer,
|
|
&FileBufferSize,
|
|
"%02u. %a - %a",
|
|
Index + 1,
|
|
TextPciClass,
|
|
TextPciSubClass
|
|
);
|
|
} else {
|
|
OcAsciiPrintBuffer (
|
|
&FileBuffer,
|
|
&FileBufferSize,
|
|
"%02u. %a",
|
|
Index + 1,
|
|
TextPciClass
|
|
);
|
|
}
|
|
|
|
//
|
|
// Dump PCI info.
|
|
//
|
|
OcAsciiPrintBuffer (
|
|
&FileBuffer,
|
|
&FileBufferSize,
|
|
"\n Vendor ID: 0x%04X, Device ID: 0x%04X, RevisionID: 0x%02X, ClassCode: 0x%02X%02X%02X",
|
|
PciDevice.Hdr.VendorId,
|
|
PciDevice.Hdr.DeviceId,
|
|
PciDevice.Hdr.RevisionID,
|
|
PciDevice.Hdr.ClassCode[2],
|
|
PciDevice.Hdr.ClassCode[1],
|
|
PciDevice.Hdr.ClassCode[0]
|
|
);
|
|
//
|
|
// Dump SubsystemVendorID and SubsystemID if the current device is not a PCI bridge.
|
|
//
|
|
if (!IS_PCI_BRIDGE (&PciDevice)) {
|
|
OcAsciiPrintBuffer (
|
|
&FileBuffer,
|
|
&FileBufferSize,
|
|
", SubsystemVendorID: 0x%04X, SubsystemID: 0x%04X",
|
|
PciDevice.Device.SubsystemVendorID,
|
|
PciDevice.Device.SubsystemID
|
|
);
|
|
}
|
|
|
|
//
|
|
// Also dump device path if possible.
|
|
//
|
|
Status = gBS->HandleProtocol (
|
|
HandleBuffer[Index],
|
|
&gEfiDevicePathProtocolGuid,
|
|
(VOID **)&PciDevicePath
|
|
);
|
|
if (!EFI_ERROR (Status)) {
|
|
TextPciDevicePath = ConvertDevicePathToText (PciDevicePath, FALSE, FALSE);
|
|
if (TextPciDevicePath != NULL) {
|
|
OcAsciiPrintBuffer (
|
|
&FileBuffer,
|
|
&FileBufferSize,
|
|
"\n DevicePath: %s",
|
|
TextPciDevicePath
|
|
);
|
|
|
|
FreePool (TextPciDevicePath);
|
|
}
|
|
}
|
|
|
|
//
|
|
// Finally, append two newlines.
|
|
//
|
|
OcAsciiPrintBuffer (&FileBuffer, &FileBufferSize, "\n\n");
|
|
}
|
|
|
|
//
|
|
// Save dumped PCI info to file.
|
|
//
|
|
if (FileBuffer != NULL) {
|
|
UnicodeSPrint (TmpFileName, sizeof (TmpFileName), L"PCIInfo.txt");
|
|
Status = OcSetFileData (Root, TmpFileName, FileBuffer, (UINT32)AsciiStrLen (FileBuffer));
|
|
DEBUG ((DEBUG_INFO, "OCDM: Dumped PCI info - %r\n", Status));
|
|
|
|
FreePool (FileBuffer);
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|