mirror of
https://github.com/acidanthera/OpenCorePkg.git
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130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/** @file
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Copyright (C) 2021, vit9696. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Uefi.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciIo.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/OcDeviceMiscLib.h>
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#include "PciExtInternal.h"
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VOID
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ActivateHpetSupport (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN HandleCount;
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EFI_HANDLE *HandleBuffer;
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UINTN Index;
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EFI_PCI_IO_PROTOCOL *PciIo;
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PCI_CLASSCODE ClassCode;
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UINT32 Rcba;
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UINT32 Hptc;
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiPciIoProtocolGuid,
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NULL,
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&HandleCount,
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&HandleBuffer
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_INFO, "OCDM: No PCI devices for HPET support - %r\n", Status));
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return;
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}
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for (Index = 0; Index < HandleCount; ++Index) {
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Status = gBS->HandleProtocol (
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HandleBuffer[Index],
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&gEfiPciIoProtocolGuid,
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(VOID **)&PciIo
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);
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if (EFI_ERROR (Status)) {
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continue;
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}
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint8,
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PCI_CLASSCODE_OFFSET,
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sizeof (PCI_CLASSCODE) / sizeof (UINT8),
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&ClassCode
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);
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if (EFI_ERROR (Status)) {
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continue;
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}
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if ((ClassCode.BaseCode == PCI_CLASS_BRIDGE) && (ClassCode.SubClassCode == PCI_CLASS_BRIDGE_ISA)) {
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Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, PCI_BRIDGE_RCBA_OFFSET, 1, &Rcba);
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if (EFI_ERROR (Status)) {
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continue;
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}
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DEBUG ((
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DEBUG_INFO,
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"OCDM: Discovered RCBA device at %u/%u at 0x%X\n",
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(UINT32)(Index + 1),
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(UINT32)HandleCount,
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Rcba
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));
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//
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// Disabled completely. Ignore.
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//
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if ((Rcba & PCI_BRIDGE_RCBA_ADDRESS_MASK) == 0) {
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continue;
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}
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//
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// Disabled access. Try to enable.
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//
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if ((Rcba & PCI_BRIDGE_RCBA_ACCESS_ENABLE) == 0) {
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Rcba |= PCI_BRIDGE_RCBA_ACCESS_ENABLE;
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, PCI_BRIDGE_RCBA_OFFSET, 1, &Rcba);
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}
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Rcba &= PCI_BRIDGE_RCBA_ADDRESS_MASK;
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Hptc = MmioRead32 (Rcba + RCBA_HTPC_REGISTER);
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DEBUG ((
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DEBUG_INFO,
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"OCDM: Discovered HPTC register with 0x%X value\n",
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Hptc
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));
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if ((Hptc & RCBA_HTPC_HPET_ENABLE) == 0) {
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MmioWrite32 (Rcba + RCBA_HTPC_REGISTER, Hptc | RCBA_HTPC_HPET_ENABLE);
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Hptc = MmioRead32 (Rcba + RCBA_HTPC_REGISTER);
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DEBUG ((
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DEBUG_INFO,
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"OCDM: Updated HPTC register with HPET has 0x%X value\n",
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Hptc
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));
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}
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}
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}
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}
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