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43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/** @file
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Copyright (C) 2021, vit9696. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-3-Clause
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**/
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#ifndef NVIDIA_MCP_MEMORY_CONTROLLER_H
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#define NVIDIA_MCP_MEMORY_CONTROLLER_H
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/**
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I/O port to obtain current DDR frequency on NVIDIA nForce MCP89
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and possibly others. Example value: 1066666664.
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**/
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#define R_NVIDIA_MCP89_DDR_PLL 0x580
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/**
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MMIO base to NVIDIA nForce MCP79 and MCP89 memory controller.
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**/
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#define B_NVIDIA_MCP_MC_BASE 0xF001B000
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/**
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Common PCI identifiers for nForce MCP79 and MCP89 memory controllers.
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**/
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#define V_NVIDIA_MCP_MC_VENDOR 0x10DE
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#define V_NVIDIA_MCP79_MC_DEVICE 0x0A89
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#define V_NVIDIA_MCP89_MC_DEVICE 0x0D69
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/**
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MCP79 and MCP89 memory controller registers, not much is known.
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**/
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#define R_NVIDIA_MCP_MC_UN44 0x44
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#define R_NVIDIA_MCP_MC_MCPC 0x48
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#define R_NVIDIA_MCP_MC_UN78 0x78
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#define R_NVIDIA_MCP_MC_MPLM 0xC8
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#define R_NVIDIA_MCP_MC_MPLN 0xC9
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#define NVIDIA_MCP79_GET_FSB_FREQUENCY_DIVIDEND(Un44, Un78) \
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(25000000ULL * (((Un44) >> 9U) & 0xFFU) * (((Un78) >> 8U) & 0xFFU))
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#define NVIDIA_MCP79_GET_FSB_FREQUENCY_DIVISOR(Un44, Un78) \
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(((Un44) & 0xFFU) * ((Un78) & 0xFFU) * (1 << (((Un44) >> 26U) & 3U)))
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#endif // NVIDIA_MCP_MEMORY_CONTROLLER_H
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