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119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/** @file
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Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface).
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Conventions:
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Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PTT_HCI_REGS_H_
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#define _PTT_HCI_REGS_H_
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//
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// FTPM HCI register base address
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//
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#define R_PTT_HCI_BASE_ADDRESS_A 0xFED40000
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#define R_PTT_HCI_BASE_ADDRESS_B 0xFED70000
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//
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// FTPM HCI Control Area
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//
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#define R_PTT_LOCALITY_STATE 0x00
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#define R_TPM_LOCALITY_CONTROL 0X08
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#define R_TPM_LOCALITY_STATUS 0x0C
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#define R_TPM_INTERFACE_ID 0x30
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#define R_CRB_CONTROL_EXT 0x38
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#define R_CRB_CONTROL_REQ 0x40
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#define R_CRB_CONTROL_STS 0x44
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#define R_CRB_CONTROL_CANCEL 0x48
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#define R_CRB_CONTROL_START 0x4C
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#define R_CRB_CONTROL_INT 0x50
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#define R_CRB_CONTROL_CMD_SIZE 0x58
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#define R_CRB_CONTROL_CMD_LOW 0x5C
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#define R_CRB_CONTROL_CMD_HIGH 0x60
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#define R_CRB_CONTROL_RESPONSE_SIZE 0x64
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#define R_CRB_CONTROL_RESPONSE_ADDR 0x68
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//
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// R_CRB_CONTROL_STS Bits
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//
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#define B_CRB_CONTROL_STS_TPM_STATUS 0x00000001 ///< BIT0
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#define B_CRB_CONTROL_STS_TPM_IDLE 0x00000002 ///< BIT1
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//
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// R_CRB_CONTROL_REQ Bits
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//
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#define B_R_CRB_CONTROL_REQ_COMMAND_READY 0x00000001 ///< BIT0
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#define B_R_CRB_CONTROL_REQ_GO_IDLE 0x00000002 ///< BIT1
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//
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// R_CRB_CONTROL_START Bits
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//
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#define B_CRB_CONTROL_START 0x00000001 ///< BIT0
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//
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// R_TPM_LOCALITY_STATUS Bits
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//
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#define B_CRB_LOCALITY_STS_GRANTED 0x00000001 ///< BIT0
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#define B_CRB_LOCALITY_STS_BEEN_SEIZED 0x00000002 ///< BIT1
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//
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// R_TPM_LOCALITY_CONTROL Bits
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//
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#define B_CRB_LOCALITY_CTL_REQUEST_ACCESS 0x00000001 ///< BIT0
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#define B_CRB_LOCALITY_CTL_RELINQUISH 0x00000002 ///< BIT1
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#define B_CRB_LOCALITY_CTL_SEIZE 0x00000004 ///< BIT2
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//
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// R_PTT_LOCALITY_STATE Bits
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//
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#define B_CRB_LOCALITY_STATE_TPM_ESTABLISHED 0x00000001 ///< BIT0
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#define B_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED 0x00000002 ///< BIT1
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#define B_CRB_LOCALITY_STATE_REGISTER_VALID 0x00000080 ///< BIT7
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//
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// R_PTT_LOCALITY_STATE Mask Values
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//
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#define V_CRB_LOCALITY_STATE_ACTIVE_LOC_MASK 0x0000001C /// Bits [4:2]
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//
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// Value written to R_PTT_HCI_CMD and CA_START
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// to indicate that a command is available for processing
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//
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#define V_PTT_HCI_COMMAND_AVAILABLE_START 0x00000001
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#define V_PTT_HCI_COMMAND_AVAILABLE_CMD 0x00000000
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#define V_PTT_HCI_BUFFER_ADDRESS_RDY 0x00000003
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//
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// Ignore bit setting mask for WaitRegisterBits
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//
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#define V_PTT_HCI_IGNORE_BITS 0x00000000
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//
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// All bits clear mask for WaitRegisterBits
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//
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#define V_PTT_HCI_ALL_BITS_CLEAR 0xFFFFFFFF
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#define V_PTT_HCI_START_CLEAR 0x00000001
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//
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// Max FTPM command/reponse buffer length
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//
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#define S_PTT_HCI_CRB_LENGTH 3968 ///< 0xFED40080:0xFED40FFF = 3968 Bytes
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#endif
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