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111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/** @file
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Copyright (C) 2021, vit9696. All rights reserved.
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All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef PCI_EXT_INTERNAL_H
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#define PCI_EXT_INTERNAL_H
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/**
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Offset to Root Complex Base Address for a PCI bridge device.
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**/
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#define PCI_BRIDGE_RCBA_OFFSET 0xF0U
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/**
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Address bits of the Root Complex Base Address register.
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**/
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#define PCI_BRIDGE_RCBA_ADDRESS_MASK 0xFFFFC000U
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/**
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Access bit of the Root Complex Base Address register.
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**/
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#define PCI_BRIDGE_RCBA_ACCESS_ENABLE BIT0
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/**
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HTPC register in RCBA.
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**/
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#define RCBA_HTPC_REGISTER 0x3404U
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/**
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HPET enable bit in HTPC.
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**/
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#define RCBA_HTPC_HPET_ENABLE BIT7
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/**
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XHCI registers.
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**/
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#define XHC_HCCPARAMS_OFFSET 0x10
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#define XHC_NEXT_CAPABILITY_MASK 0xFF00
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#define XHC_CAPABILITY_ID_MASK 0xFF
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#define XHC_USBCMD_OFFSET 0x0 ///< USB Command Register Offset
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#define XHC_USBSTS_OFFSET 0x4 ///< USB Status Register Offset
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#define XHC_POLL_DELAY 1000
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/**
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EHCI registers.
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**/
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#define EHC_BAR_INDEX 0x0
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#define EHC_HCCPARAMS_OFFSET 0x8
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#define EHC_USBCMD_OFFSET 0x0 ///< USB Command Register Offset
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#define EHC_USBSTS_OFFSET 0x4 ///< USB Status Register Offset
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#define EHC_USBINT_OFFSET 0x8 ///< USB Interrupt Enable Register
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/**
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HDA audio class missing from Pci22.h.
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**/
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#define PCI_CLASS_MEDIA_HDA 0x03
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/**
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Offset to TCSEL register for a PCI media device.
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**/
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#define PCI_MEDIA_TCSEL_OFFSET 0x44U
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/**
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TCSEL class mask.
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**/
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#define TCSEL_CLASS_MASK 0x7U
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/**
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When the bit of Capabilities Set, it indicates that the Function supports
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operating with the BAR sized to (2^Bit) MB. Example:
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- Bit 0 is set: supports operating with the BAR sized to 1 MB
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- Bit 1 is set: supports operating with the BAR sized to 2 MB
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- Bit n is set: supports operating with the BAR sized to (2^n) MB
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**/
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#define PCI_BAR_CAP_1MB BIT0
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#define PCI_BAR_CAP_2MB BIT1
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#define PCI_BAR_CAP_4MB BIT2
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#define PCI_BAR_CAP_8MB BIT3
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#define PCI_BAR_CAP_16MB BIT4
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#define PCI_BAR_CAP_32MB BIT5
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#define PCI_BAR_CAP_64MB BIT6
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#define PCI_BAR_CAP_128MB BIT7
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#define PCI_BAR_CAP_256MB BIT8
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#define PCI_BAR_CAP_512MB BIT9
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#define PCI_BAR_CAP_1GB BIT10
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#define PCI_BAR_CAP_2GB BIT11
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#define PCI_BAR_CAP_4GB BIT12
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#define PCI_BAR_CAP_8GB BIT13
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#define PCI_BAR_CAP_16GB BIT14
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#define PCI_BAR_CAP_32GB BIT15
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#define PCI_BAR_CAP_64GB BIT16
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#define PCI_BAR_CAP_128GB BIT17
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#define PCI_BAR_CAP_256GB BIT18
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#define PCI_BAR_CAP_512GB BIT19
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/**
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Capability limit mask from BarSize (e.g. PciBar1MB).
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**/
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#define PCI_BAR_CAP_LIMIT(BarSize) ((1U << ((BarSize) + 1)) - 1)
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#endif // PCI_EXT_INTERNAL_H
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