diff --git a/Changelog.md b/Changelog.md
index 0e9cf33d..036c67ce 100644
--- a/Changelog.md
+++ b/Changelog.md
@@ -6,6 +6,8 @@ OpenCore Changelog
 - Added `InstanceIdentifier` to OpenCore and option to target `.contentVisibility` to specific instances (thx @dakanji)
 - Improved `LapicKernelPanic` quirk on legacy versions of macOS
 - Allowed `.contentVisibility` in same boot FS root locations as `.VolumeIcon.icns`, in order to survive macOS updates
+- Fixed incorrect core count on Silvermont Atom/Celeron processors
+- Fixed PM timer detection on Silvermont Atom/Celeron processors for TSC calculations
 
 #### v0.9.3
 - Added `--force-codec` option to AudioDxe, thx @xCuri0
diff --git a/Include/Intel/IndustryStandard/GenericIch.h b/Include/Intel/IndustryStandard/GenericIch.h
index 412f1f58..0f79218c 100644
--- a/Include/Intel/IndustryStandard/GenericIch.h
+++ b/Include/Intel/IndustryStandard/GenericIch.h
@@ -36,6 +36,8 @@
 
 #define V_ICH_PCI_VENDOR_ID        0x8086    ///< Intel vendor-id
 #define V_PIIX4_PMC_PCI_DEVICE_ID  0x7113    ///< Intel PIIX4 PMC device-id
+#define V_VLV_PMC_PCI_DEVICE_ID    0x0F1C    ///< Intel Valley View PMC device-id
+#define V_CHT_PMC_PCI_DEVICE_ID    0x229C    ///< Intel Bay-Trail/Cherry-Trail PMC device-id
 
 // IchAcpiCntr   Control for the ICH's ACPI Counter.
 
@@ -75,6 +77,11 @@
 #define B_ICH_PMC_BAR2_BASE_BAR     B_ICH_BAR2_BASE_BAR
 #define B_ICH_PMC_BAR2_BASE_BAR_EN  B_ICH_BAR2_BASE_BAR_EN
 
+// Intel Braswell
+
+#define R_BRSW_PMC_ACPI_BASE         0x40
+#define B_BRSW_PMC_ACPI_BASE_BAR     0xFFFFFE00
+
 // AMD Bolton (AMD Bolton Register Reference Guide 3.03)
 
 #define R_AMD_ACPI_MMIO_BASE       0xFED80000    ///< AcpiMMioAddr (3-268)
diff --git a/Library/OcCpuLib/FrequencyDetect.c b/Library/OcCpuLib/FrequencyDetect.c
index 520b57da..2f797d41 100644
--- a/Library/OcCpuLib/FrequencyDetect.c
+++ b/Library/OcCpuLib/FrequencyDetect.c
@@ -73,7 +73,12 @@ InternalGetPmTimerAddr (
     // but it is referred to as PMC I/O space, and the addressing is done through BAR2.
     // In addition to that on B360 and friends PMC controller may be just missing.
     //
-    if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNTL)) & B_ICH_LPC_ACPI_CNTL_ACPI_EN) != 0) {
+    if ((PciRead16 (PCI_ICH_LPC_ADDRESS (2)) == V_VLV_PMC_PCI_DEVICE_ID) || (PciRead16 (PCI_ICH_LPC_ADDRESS (2)) == V_CHT_PMC_PCI_DEVICE_ID)) {
+      TimerAddr = (PciRead32 (PCI_ICH_LPC_ADDRESS (R_BRSW_PMC_ACPI_BASE)) & B_BRSW_PMC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;
+      if (Type != NULL) {
+        *Type = "Braswell PMC";
+      }
+    } else if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNTL)) & B_ICH_LPC_ACPI_CNTL_ACPI_EN) != 0) {
       TimerAddr = (PciRead16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE)) & B_ICH_LPC_ACPI_BASE_BAR) + R_ACPI_PM1_TMR;
       if (Type != NULL) {
         *Type = "LPC";
diff --git a/Library/OcCpuLib/OcCpuLib.c b/Library/OcCpuLib/OcCpuLib.c
index a007433e..100beecb 100644
--- a/Library/OcCpuLib/OcCpuLib.c
+++ b/Library/OcCpuLib/OcCpuLib.c
@@ -428,6 +428,9 @@ ScanIntelProcessor (
   UINT64                                            Msr;
   CPUID_CACHE_PARAMS_EAX                            CpuidCacheEax;
   CPUID_CACHE_PARAMS_EBX                            CpuidCacheEbx;
+  CPUID_EXTENDED_TOPOLOGY_EAX                       CpuidExTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX                       CpuidExTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX                       CpuidExTopologyEcx;
   MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  PkgCstConfigControl;
   UINT16                                            CoreCount;
   CONST CHAR8                                       *TimerSourceType;
@@ -555,7 +558,6 @@ ScanIntelProcessor (
         || (Cpu->CpuGeneration == OcCpuGenerationYonahMerom)
         || (Cpu->CpuGeneration == OcCpuGenerationPenryn)
         || (Cpu->CpuGeneration == OcCpuGenerationBonnell)
-        || (Cpu->CpuGeneration == OcCpuGenerationSilvermont)
         || Cpu->Hypervisor))
   {
     AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CpuidCacheEax.Uint32, &CpuidCacheEbx.Uint32, NULL, NULL);
@@ -574,6 +576,19 @@ ScanIntelProcessor (
         Cpu->ThreadCount = Cpu->CoreCount;
       }
     }
+  } else if (Cpu->CpuGeneration == OcCpuGenerationSilvermont) {
+    //
+    // MSR 0x35 is unsupported, and CPUID leaf 4 does not give correct information on Silvermont Celeron/Atom processors.
+    // Use CPUID leaf 11 instead.
+    // No Hyperthreading on these processors, should be ok to assume logical processor count == core count.
+    //
+    // Level 0 - threads per core.
+    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &CpuidExTopologyEax.Uint32, &CpuidExTopologyEbx.Uint32, &CpuidExTopologyEcx.Uint32, NULL);
+
+    // Level 1 - total logical processor count.
+    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &CpuidExTopologyEax.Uint32, &CpuidExTopologyEbx.Uint32, &CpuidExTopologyEcx.Uint32, NULL);
+    Cpu->CoreCount   = (UINT16)GetPowerOfTwo32 (CpuidExTopologyEbx.Bits.LogicalProcessors);
+    Cpu->ThreadCount = Cpu->CoreCount;
   } else if (Cpu->CpuGeneration == OcCpuGenerationWestmere) {
     Msr              = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
     Cpu->CoreCount   = (UINT16)BitFieldRead64 (Msr, 16, 19);
@@ -1357,7 +1372,6 @@ InternalDetectIntelProcessorGeneration (
         break;
       case CPU_MODEL_BONNELL:
       case CPU_MODEL_BONNELL_MID:
-      case CPU_MODEL_AVOTON: /* perhaps should be distinct */
         CpuGeneration = OcCpuGenerationBonnell;
         break;
       case CPU_MODEL_DALES_32NM:
@@ -1372,6 +1386,7 @@ InternalDetectIntelProcessorGeneration (
       case CPU_MODEL_SILVERMONT:
       case CPU_MODEL_GOLDMONT:
       case CPU_MODEL_AIRMONT:
+      case CPU_MODEL_AVOTON:
         CpuGeneration = OcCpuGenerationSilvermont;
         break;
       case CPU_MODEL_IVYBRIDGE: