diff --git a/Include/Guid/LiluVariables.h b/Include/Guid/LiluVariables.h
new file mode 100644
index 00000000..4d23b4e1
--- /dev/null
+++ b/Include/Guid/LiluVariables.h
@@ -0,0 +1,38 @@
+/** @file
+ Lilu specific GUIDs for UEFI Variable Storage, version 1.0.
+
+Copyright (c) 2018, vit9696. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// 2660DD78-81D2-419D-8138-7B1F363F79A6
+// This GUID is specifically used for normal variable access by Lilu kernel extension and its plugins.
+//
+#define LILU_NORMAL_VARIABLE_GUID \
+ { 0x2660DD78, 0x81D2, 0x419D, { 0x81, 0x38, 0x7B, 0x1F, 0x36, 0x3F, 0x79, 0xA6 } }
+
+//
+// E09B9297-7928-4440-9AAB-D1F8536FBF0A
+// This GUID is specifically used for reading variables by Lilu kernel extension and its plugins.
+// Any writes to this GUID should be prohibited via EFI_RUNTIME_SERVICES after EXIT_BOOT_SERVICES.
+// The expected return code on variable write is EFI_SECURITY_VIOLATION.
+//
+#define LILU_READ_ONLY_VARIABLE_GUID \
+ { 0xE09B9297, 0x7928, 0x4440, { 0x9A, 0xAB, 0xD1, 0xF8, 0x53, 0x6F, 0xBF, 0x0A } }
+
+//
+// F0B9AF8F-2222-4840-8A37-ECF7CC8C12E1
+// This GUID is specifically used for reading variables by Lilu and plugins.
+// Any reads from this GUID should be prohibited via EFI_RUNTIME_SERVICES after EXIT_BOOT_SERVICES.
+// The expected return code on variable read is EFI_SECURITY_VIOLATION.
+//
+#define LILU_WRITE_ONLY_VARIABLE_GUID \
+ { 0xF0B9AF8F, 0x2222, 0x4840, { 0x8A, 0x37, 0xEC, 0xF7, 0xCC, 0x8C, 0x12, 0xE1 } }
diff --git a/Include/Library/OcRtcLib.h b/Include/Library/OcRtcLib.h
new file mode 100644
index 00000000..1ebf0a72
--- /dev/null
+++ b/Include/Library/OcRtcLib.h
@@ -0,0 +1,52 @@
+/** @file
+
+OcRtcLib - library with RTC I/O functions
+
+Copyright (c) 2017-2018, vit9696
+
+All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OC_RTC_LIB_H
+#define OC_RTC_LIB_H
+
+//
+// Standard interface, available on most Intel chipsets
+//
+
+UINT8
+OcRtcRead (
+ IN UINT8 Offset
+ );
+
+VOID
+OcRtcWrite (
+ IN UINT8 Offset,
+ IN UINT8 Value
+ );
+
+//
+// Modern faster interface, available on IvyBridge or newer
+//
+
+UINT8
+OcRtcReadIvy (
+ IN UINT8 Offset
+ );
+
+VOID
+OcRtcWriteIvy (
+ IN UINT8 Offset,
+ IN UINT8 Value
+ );
+
+#endif // OC_RTC_LIB_H
diff --git a/Library/OcRtcLib/OcRtcLib.c b/Library/OcRtcLib/OcRtcLib.c
new file mode 100644
index 00000000..deaab455
--- /dev/null
+++ b/Library/OcRtcLib/OcRtcLib.c
@@ -0,0 +1,139 @@
+/** @file
+
+OcRtcLib - library with RTC I/O functions
+
+Copyright (c) 2017-2018, vit9696
+
+All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+
+//
+// Available on all platforms, requires NMI bit handling.
+//
+#define R_PCH_RTC_INDEX 0x70
+#define R_PCH_RTC_TARGET 0x71
+#define R_PCH_RTC_EXT_INDEX 0x72
+#define R_PCH_RTC_EXT_TARGET 0x73
+
+//
+// Available on Ivy Bridge and newer. Ignores NMI bit.
+//
+#define R_PCH_RTC_INDEX_ALT 0x74
+#define R_PCH_RTC_TARGET_ALT 0x75
+#define R_PCH_RTC_EXT_INDEX_ALT 0x76
+#define R_PCH_RTC_EXT_TARGET_ALT 0x77
+
+//
+// RTC Memory bank size
+//
+#define RTC_BANK_SIZE 0x80
+
+//
+// RTC INDEX bit mask
+//
+#define RTC_DATA_MASK 0x7F
+#define RTC_NMI_MASK 0x80
+
+UINT8
+OcRtcRead (
+ IN UINT8 Offset
+ )
+{
+ UINT8 RtcIndexPort;
+ UINT8 RtcDataPort;
+ UINT8 RtcIndexNmi;
+
+ if (Offset < RTC_BANK_SIZE) {
+ RtcIndexPort = R_PCH_RTC_INDEX;
+ RtcDataPort = R_PCH_RTC_TARGET;
+ } else {
+ RtcIndexPort = R_PCH_RTC_EXT_INDEX;
+ RtcDataPort = R_PCH_RTC_EXT_TARGET;
+ }
+
+ RtcIndexNmi = IoRead8 (RtcIndexPort) & RTC_NMI_MASK;
+ IoWrite8 (RtcIndexPort, (Offset & RTC_DATA_MASK) | RtcIndexNmi);
+ return IoRead8 (RtcDataPort);
+}
+
+VOID
+OcRtcWrite (
+ IN UINT8 Offset,
+ IN UINT8 Value
+ )
+{
+ UINT8 RtcIndexPort;
+ UINT8 RtcDataPort;
+ UINT8 RtcIndexNmi;
+
+ if (Offset < RTC_BANK_SIZE) {
+ RtcIndexPort = R_PCH_RTC_INDEX;
+ RtcDataPort = R_PCH_RTC_TARGET;
+ } else {
+ RtcIndexPort = R_PCH_RTC_EXT_INDEX;
+ RtcDataPort = R_PCH_RTC_EXT_TARGET;
+ }
+
+ RtcIndexNmi = IoRead8 (RtcIndexPort) & RTC_NMI_MASK;
+ IoWrite8 (RtcIndexPort, (Offset & RTC_DATA_MASK) | RtcIndexNmi);
+ IoWrite8 (RtcDataPort, Value);
+}
+
+UINT8
+OcRtcReadIvy (
+ IN UINT8 Offset
+ )
+{
+ UINT8 RtcIndexPort;
+ UINT8 RtcDataPort;
+
+ //
+ // CMOS access registers (using alternative access not to handle NMI bit)
+ //
+ if (Offset < RTC_BANK_SIZE) {
+ RtcIndexPort = R_PCH_RTC_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_TARGET_ALT;
+ } else {
+ RtcIndexPort = R_PCH_RTC_EXT_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_EXT_TARGET_ALT;
+ }
+
+ IoWrite8 (RtcIndexPort, Offset & RTC_DATA_MASK);
+ return IoRead8 (RtcDataPort);
+}
+
+VOID
+OcRtcWriteIvy (
+ IN UINT8 Offset,
+ IN UINT8 Value
+ )
+{
+ UINT8 RtcIndexPort;
+ UINT8 RtcDataPort;
+
+ //
+ // CMOS access registers (using alternative access not to handle NMI bit)
+ //
+ if (Offset < RTC_BANK_SIZE) {
+ RtcIndexPort = R_PCH_RTC_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_TARGET_ALT;
+ } else {
+ RtcIndexPort = R_PCH_RTC_EXT_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_EXT_TARGET_ALT;
+ }
+
+ IoWrite8 (RtcIndexPort, Offset & RTC_DATA_MASK);
+ IoWrite8 (RtcDataPort, Value);
+}
diff --git a/Library/OcRtcLib/OcRtcLib.inf b/Library/OcRtcLib/OcRtcLib.inf
new file mode 100644
index 00000000..798c43ae
--- /dev/null
+++ b/Library/OcRtcLib/OcRtcLib.inf
@@ -0,0 +1,39 @@
+## @file
+# OcRtcLib - library with RTC I/O functions
+#
+# Copyright (c) 2017-2018, vit9696
+#
+# All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OcRtcLib
+ FILE_GUID = DDFDC74D-E1AC-4A9F-A667-5DB8B6D8A67E
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OcRtcLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
+
+
+#
+# VALID_ARCHITECTURES = X64
+#
+
+[Sources]
+ OcRtcLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ OcSupportPkg/OcSupportPkg.dec
+
+[LibraryClasses]
+ IoLib