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Docs: Add some ACPI samples

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vit9696 2019-04-10 12:42:46 +03:00
parent 6f91e974db
commit 69f1cafc43
4 changed files with 290 additions and 0 deletions
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81
Docs/AcpiSamples/SSDT-EC-USBX.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190215 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of iASLtpfpGZ.aml, Wed Apr 10 10:40:54 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000125 (293)
* Revision 0x02
* Checksum 0x1E
* OEM ID "APPLE "
* OEM Table ID "SsdtEC"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20161210 (538317328)
*/
DefinitionBlock ("", "SSDT", 2, "APPLE ", "SsdtEC", 0x00001000)
{
External (_SB_.PCI0.LPCB, DeviceObj)
External (UMAP, IntObj)
Scope (\_SB)
{
Device (USBX)
{
Name (_ADR, Zero) // _ADR: Address
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x03 // .
})
}
Return (Package (0x08)
{
"kUSBSleepPowerSupply",
0x0640,
"kUSBSleepPortCurrentLimit",
0x0A8C,
"kUSBWakePowerSupply",
0x0640,
"kUSBWakePortCurrentLimit",
0x0A8C
})
}
}
Scope (\_SB.PCI0.LPCB)
{
Device (EC)
{
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
IO (Decode16,
0x0062, // Range Minimum
0x0062, // Range Maximum
0x00, // Alignment
0x01, // Length
)
IO (Decode16,
0x0066, // Range Minimum
0x0066, // Range Maximum
0x00, // Alignment
0x01, // Length
)
})
Name (_GPE, 0x17) // _GPE: General Purpose Events
}
}
}
}

51
Docs/AcpiSamples/SSDT-EC.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190215 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of iASLTMpFbq.aml, Wed Apr 10 11:34:45 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000008C (140)
* Revision 0x02
* Checksum 0x46
* OEM ID "APPLE "
* OEM Table ID "SsdtEC"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20161210 (538317328)
*/
DefinitionBlock ("", "SSDT", 2, "APPLE ", "SsdtEC", 0x00001000)
{
External (_SB_.PCI0.LPCB, DeviceObj)
External (UMAP, IntObj)
Scope (\_SB.PCI0.LPCB)
{
Device (EC)
{
Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
IO (Decode16,
0x0062, // Range Minimum
0x0062, // Range Maximum
0x00, // Alignment
0x01, // Length
)
IO (Decode16,
0x0066, // Range Minimum
0x0066, // Range Maximum
0x00, // Alignment
0x01, // Length
)
})
Name (_GPE, 0x17) // _GPE: General Purpose Events
}
}
}

68
Docs/AcpiSamples/SSDT-PLUG.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190215 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of iASLspH90v.aml, Wed Apr 10 10:41:25 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000000A6 (166)
* Revision 0x02
* Checksum 0xF0
* OEM ID "CpuRef"
* OEM Table ID "CpuPlug"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20160729 (538314537)
*/
DefinitionBlock ("", "SSDT", 2, "CpuRef", "CpuPlug", 0x00003000)
{
External (_PR_.CPU0, ProcessorObj)
Scope (\_PR.CPU0)
{
Method (DTGP, 5, NotSerialized)
{
If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))
{
If ((Arg1 == One))
{
If ((Arg2 == Zero))
{
Arg4 = Buffer (One)
{
0x03 // .
}
Return (One)
}
If ((Arg2 == One))
{
Return (One)
}
}
}
Arg4 = Buffer (One)
{
0x00 // .
}
Return (Zero)
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
"plugin-type",
One
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
}

90
Docs/AcpiSamples/SSDT-SBUS-MCHC.dsl Normal file
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/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190215 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of iASLgWfJxu.aml, Wed Apr 10 10:23:44 2019
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000108 (264)
* Revision 0x02
* Checksum 0xFD
* OEM ID "hack"
* OEM Table ID "MCHCSBUS"
* OEM Revision 0x00000000 (0)
* Compiler ID "INTL"
* Compiler Version 0x20190215 (538509845)
*/
DefinitionBlock ("", "SSDT", 2, "hack", "MCHCSBUS", 0x00000000)
{
External (_SB_.PCI0, DeviceObj)
External (_SB_.PCI0.SBUS.BUS0, DeviceObj)
Scope (_SB.PCI0)
{
Device (MCHC)
{
Name (_ADR, Zero) // _ADR: Address
}
}
Device (_SB.PCI0.SBUS.BUS0)
{
Name (_CID, "smbus") // _CID: Compatible ID
Name (_ADR, Zero) // _ADR: Address
Device (DVL0)
{
Name (_ADR, 0x57) // _ADR: Address
Name (_CID, "diagsvault") // _CID: Compatible ID
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If (!Arg2)
{
Return (Buffer (One)
{
0x57 // W
})
}
Return (Package (0x02)
{
"address",
0x57
})
}
}
}
Method (DTGP, 5, NotSerialized)
{
If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))
{
If ((Arg1 == One))
{
If ((Arg2 == Zero))
{
Arg4 = Buffer (One)
{
0x03 // .
}
Return (One)
}
If ((Arg2 == One))
{
Return (One)
}
}
}
Arg4 = Buffer (One)
{
0x00 // .
}
Return (Zero)
}
}