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266 lines
8.9 KiB
C
266 lines
8.9 KiB
C
/* mbed Microcontroller Library
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* Copyright (C) 2008-2009 ARM Limited. All rights reserved.
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*
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* ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
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* based on core_cm3.h, V1.20
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*/
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#ifndef __ARM7_CORE_H__
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#define __ARM7_CORE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
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#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
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#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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#define __CORTEX_M (0x03) /*!< Cortex core */
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/**
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* Lint configuration \n
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* ----------------------- \n
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*
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* The following Lint messages will be suppressed and not shown: \n
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* \n
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* --- Error 10: --- \n
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* register uint32_t __regBasePri __asm("basepri"); \n
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* Error 10: Expecting ';' \n
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* \n
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* --- Error 530: --- \n
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* return(__regBasePri); \n
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* Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
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* \n
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* --- Error 550: --- \n
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* __regBasePri = (basePri & 0x1ff); \n
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* } \n
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* Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
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* \n
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* --- Error 754: --- \n
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* uint32_t RESERVED0[24]; \n
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* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
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* \n
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* --- Error 750: --- \n
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* #define __CM3_CORE_H__ \n
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* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
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* \n
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* --- Error 528: --- \n
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* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
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* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
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* \n
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* --- Error 751: --- \n
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* } InterruptType_Type; \n
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* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
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* \n
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* \n
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* Note: To re-enable a Message, insert a space before 'lint' * \n
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*
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*/
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/*lint -save */
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/*lint -e10 */
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/*lint -e530 */
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/*lint -e550 */
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/*lint -e754 */
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/*lint -e750 */
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/*lint -e528 */
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/*lint -e751 */
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#include <stdint.h> /* Include standard types */
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#if defined ( __CC_ARM )
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/**
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* @brief Return the Main Stack Pointer (current ARM7 stack)
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*
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* @param none
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* @return uint32_t Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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extern uint32_t __get_MSP(void);
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#endif
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#if defined (__ICCARM__)
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#include <intrinsics.h> /* IAR Intrinsics */
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#endif
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
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#endif
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typedef struct
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{
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uint32_t IRQStatus;
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uint32_t FIQStatus;
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uint32_t RawIntr;
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uint32_t IntSelect;
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uint32_t IntEnable;
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uint32_t IntEnClr;
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uint32_t SoftInt;
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uint32_t SoftIntClr;
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uint32_t Protection;
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uint32_t SWPriorityMask;
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uint32_t RESERVED0[54];
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uint32_t VectAddr[32];
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uint32_t RESERVED1[32];
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uint32_t VectPriority[32];
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uint32_t RESERVED2[800];
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uint32_t Address;
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} NVIC_TypeDef;
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#define NVIC_BASE (0xFFFFF000)
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#define NVIC (( NVIC_TypeDef *) NVIC_BASE)
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/**
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* IO definitions
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*
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* define access restrictions to peripheral registers
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< defines 'read only' permissions */
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#else
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#define __I volatile const /*!< defines 'read only' permissions */
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#endif
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#define __O volatile /*!< defines 'write only' permissions */
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#define __IO volatile /*!< defines 'read / write' permissions */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#endif
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/* ################### Compiler specific Intrinsics ########################### */
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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#define __enable_fault_irq __enable_fiq
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#define __disable_fault_irq __disable_fiq
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#define __NOP __nop
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//#define __WFI __wfi
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//#define __WFE __wfe
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//#define __SEV __sev
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//#define __ISB() __isb(0)
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//#define __DSB() __dsb(0)
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//#define __DMB() __dmb(0)
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//#define __REV __rev
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//#define __RBIT __rbit
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#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
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#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
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#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
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#define __STREXB(value, ptr) __strex(value, ptr)
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#define __STREXH(value, ptr) __strex(value, ptr)
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#define __STREXW(value, ptr) __strex(value, ptr)
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#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
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LPC_VIC->IntEnClr = 0xffffffff
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#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
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#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
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#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
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#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
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#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
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#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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static __INLINE void __enable_irq() {
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unsigned long temp;
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__asm__ __volatile__("mrs %0, cpsr\n"
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"bic %0, %0, #0x80\n"
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"msr cpsr_c, %0"
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: "=r" (temp)
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:
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: "memory");
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}
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static __INLINE void __disable_irq() {
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unsigned long old,temp;
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__asm__ __volatile__("mrs %0, cpsr\n"
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"orr %1, %0, #0xc0\n"
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"msr cpsr_c, %1"
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: "=r" (old), "=r" (temp)
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:
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: "memory");
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// return (old & 0x80) == 0;
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}
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static __INLINE void __NOP() { __ASM volatile ("nop"); }
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#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
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/* TASKING carm specific functions */
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all instrinsics,
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* Including the CMSIS ones.
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*/
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#endif
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/**
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* @brief Enable Interrupt in NVIC Interrupt Controller
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*
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* @param IRQn_Type IRQn specifies the interrupt number
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* @return none
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*
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* Enable a device specific interupt in the NVIC interrupt controller.
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* The interrupt number cannot be a negative value.
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*/
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static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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NVIC->IntEnable = 1 << (uint32_t)IRQn;
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}
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/**
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* @brief Disable the interrupt line for external interrupt specified
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*
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* @param IRQn_Type IRQn is the positive number of the external interrupt
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* @return none
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*
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* Disable a device specific interupt in the NVIC interrupt controller.
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* The interrupt number cannot be a negative value.
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*/
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static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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{
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NVIC->IntEnClr = 1 << (uint32_t)IRQn;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARM7_CORE_H__ */
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/*lint -restore */
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