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1331 lines
69 KiB
C
1331 lines
69 KiB
C
/***************************************************************************//**
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* @file em_ldma.h
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* @brief Direct memory access (LDMA) API
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* @version 4.2.1
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
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*******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.@n
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.@n
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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* obligation to support this Software. Silicon Labs is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Silicon Labs will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __SILICON_LABS_EM_LDMA_H__
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#define __SILICON_LABS_EM_LDMA_H__
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#include "em_device.h"
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#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup EM_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup LDMA
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/**
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* This value controls the number of unit data transfers per arbitration
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* cycle, providing a means to balance DMA channels' load on the controller.
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*/
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typedef enum
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{
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ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */
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ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */
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ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */
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ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */
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ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */
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ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */
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ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */
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ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */
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ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */
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} LDMA_CtrlBlockSize_t;
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/** DMA structure type. */
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typedef enum
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{
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ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */
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ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
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ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */
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} LDMA_CtrlStructType_t;
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/** DMA transfer block or cycle selector. */
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typedef enum
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{
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ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */
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ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */
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} LDMA_CtrlReqMode_t;
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/** Source address increment unit size. */
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typedef enum
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{
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ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */
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ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */
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ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
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ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment the source address. */
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} LDMA_CtrlSrcInc_t;
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/** DMA transfer unit size. */
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typedef enum
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{
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ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */
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ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
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ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */
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} LDMA_CtrlSize_t;
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/** Destination address increment unit size. */
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typedef enum
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{
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ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */
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ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */
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ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
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ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment the destination address. */
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} LDMA_CtrlDstInc_t;
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/** Source addressing mode. */
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typedef enum
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{
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ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
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ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
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} LDMA_CtrlSrcAddrMode_t;
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/** Destination addressing mode. */
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typedef enum
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{
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ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
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ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
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} LDMA_CtrlDstAddrMode_t;
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/** DMA linkload address mode. */
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typedef enum
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{
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ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */
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ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement releative address. */
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} LDMA_LinkMode_t;
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/** Insert extra arbitration slots to increase channel arbitration priority. */
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typedef enum
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{
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ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */
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ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */
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ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */
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ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */
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} LDMA_CfgArbSlots_t;
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/** Source address increment sign. */
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typedef enum
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{
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ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
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ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */
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} LDMA_CfgSrcIncSign_t;
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/** Destination address increment sign. */
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typedef enum
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{
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ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
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ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */
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} LDMA_CfgDstIncSign_t;
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/** Peripherals that can trigger LDMA transfers. */
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typedef enum
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{
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ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
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#if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
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ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
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ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
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ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
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ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
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ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
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ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
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ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
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ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
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ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
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ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
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ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
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ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
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ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
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ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
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ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
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ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
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ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
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ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
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ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
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ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
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ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
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ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
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ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
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ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
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ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
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ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
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ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
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ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
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ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
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ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
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ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
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ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
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ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
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ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
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ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
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ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
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ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
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ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
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ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
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ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
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ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT.
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#endif
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#if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
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ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1 ///< Trig on USART1_TXEMPTY.
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#endif
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} LDMA_PeripheralSignal_t;
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/**
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* @brief
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* DMA descriptor.
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* @details
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* The LDMA DMA controller supports three different DMA descriptors. Each
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* consist of four WORD's which map directly onto hw control registers for a
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* given DMA channel. The three descriptor types are XFER, SYNC and WRI.
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* Refer to the reference manual for further information.
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*/
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typedef union
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{
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/**
|
|
* TRANSFER DMA descriptor, this is the only descriptor type which can be
|
|
* used to start a DMA transfer.
|
|
*/
|
|
struct
|
|
{
|
|
uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
|
|
uint32_t reserved0 : 1;
|
|
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
|
|
uint32_t xferCnt : 11; /**< Transfer count minus one. */
|
|
uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
|
|
uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */
|
|
uint32_t doneIfs : 1; /**< Generate interrupt when done. */
|
|
uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
|
|
uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
|
|
uint32_t ignoreSrec : 1; /**< Ignore single requests. */
|
|
uint32_t srcInc : 2; /**< Source address increment unit size. */
|
|
uint32_t size : 2; /**< DMA transfer unit size. */
|
|
uint32_t dstInc : 2; /**< Destination address increment unit size. */
|
|
uint32_t srcAddrMode: 1; /**< Source addressing mode. */
|
|
uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
|
|
|
|
uint32_t srcAddr; /**< DMA source address. */
|
|
uint32_t dstAddr; /**< DMA destination address. */
|
|
|
|
uint32_t linkMode : 1; /**< Select absolute or relative link address.*/
|
|
uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
|
|
int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
|
|
} xfer;
|
|
|
|
/** SYNCHRONIZE DMA descriptor, used for intra channel transfer
|
|
* syncronization.
|
|
*/
|
|
struct
|
|
{
|
|
uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */
|
|
uint32_t reserved0 : 1;
|
|
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
|
|
uint32_t xferCnt : 11; /**< Transfer count minus one. */
|
|
uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
|
|
uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */
|
|
uint32_t doneIfs : 1; /**< Generate interrupt when done. */
|
|
uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
|
|
uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
|
|
uint32_t ignoreSrec : 1; /**< Ignore single requests. */
|
|
uint32_t srcInc : 2; /**< Source address increment unit size. */
|
|
uint32_t size : 2; /**< DMA transfer unit size. */
|
|
uint32_t dstInc : 2; /**< Destination address increment unit size. */
|
|
uint32_t srcAddrMode: 1; /**< Source addressing mode. */
|
|
uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
|
|
|
|
uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */
|
|
uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register*/
|
|
uint32_t reserved3 : 16;
|
|
uint32_t matchVal : 8; /**< Sync trig match value. */
|
|
uint32_t matchEn : 8; /**< Sync trig match enable. */
|
|
uint32_t reserved4 : 16;
|
|
|
|
uint32_t linkMode : 1; /**< Select absolute or relative link address.*/
|
|
uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
|
|
int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
|
|
} sync;
|
|
|
|
/** WRITE DMA descriptor, used for write immediate operations. */
|
|
struct
|
|
{
|
|
uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type.*/
|
|
uint32_t reserved0 : 1;
|
|
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
|
|
uint32_t xferCnt : 11; /**< Transfer count minus one. */
|
|
uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
|
|
uint32_t blockSize : 4; /**< Number of unit transfers per arb. cycle. */
|
|
uint32_t doneIfs : 1; /**< Generate interrupt when done. */
|
|
uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
|
|
uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
|
|
uint32_t ignoreSrec : 1; /**< Ignore single requests. */
|
|
uint32_t srcInc : 2; /**< Source address increment unit size. */
|
|
uint32_t size : 2; /**< DMA transfer unit size. */
|
|
uint32_t dstInc : 2; /**< Destination address increment unit size. */
|
|
uint32_t srcAddrMode: 1; /**< Source addressing mode. */
|
|
uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
|
|
|
|
uint32_t immVal; /**< Data to be written at dstAddr. */
|
|
uint32_t dstAddr; /**< DMA write destination address. */
|
|
|
|
uint32_t linkMode : 1; /**< Select absolute or relative link address.*/
|
|
uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
|
|
int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
|
|
} wri;
|
|
} LDMA_Descriptor_t;
|
|
|
|
/** @brief LDMA initialization configuration structure. */
|
|
typedef struct
|
|
{
|
|
uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator.*/
|
|
uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
|
|
uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */
|
|
uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */
|
|
} LDMA_Init_t;
|
|
|
|
/**
|
|
* @brief
|
|
* DMA transfer configuration structure.
|
|
* @details
|
|
* This struct configures all aspects of a DMA transfer.
|
|
*/
|
|
typedef struct
|
|
{
|
|
uint32_t ldmaReqSel; /**< Selects DMA trigger source. */
|
|
uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
|
|
uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */
|
|
uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */
|
|
uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */
|
|
bool ldmaReqDis; /**< Mask the PRS trigger input. */
|
|
bool ldmaDbgHalt; /**< Dis. DMA trig when cpu is halted. */
|
|
uint8_t ldmaCfgArbSlots; /**< Arbitration slot number. */
|
|
uint8_t ldmaCfgSrcIncSign; /**< Source addr. increment sign. */
|
|
uint8_t ldmaCfgDstIncSign; /**< Dest. addr. increment sign. */
|
|
uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */
|
|
} LDMA_TransferCfg_t;
|
|
|
|
|
|
/*******************************************************************************
|
|
************************** STRUCT INITIALIZERS ****************************
|
|
******************************************************************************/
|
|
|
|
|
|
/** @brief Default DMA initialization structure. */
|
|
#define LDMA_INIT_DEFAULT \
|
|
{ \
|
|
.ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT, /* Fixed priority arbitration. */ \
|
|
.ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
|
|
.ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
|
|
.ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* Generic DMA transfer configuration for memory to memory transfers.
|
|
*/
|
|
#define LDMA_TRANSFER_CFG_MEMORY() \
|
|
{ \
|
|
0, 0, 0, 0, 0, \
|
|
false, false, ldmaCfgArbSlotsAs1, \
|
|
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* Generic DMA transfer configuration for looped memory to memory transfers.
|
|
*/
|
|
#define LDMA_TRANSFER_CFG_MEMORY_LOOP( loopCnt) \
|
|
{ \
|
|
0, 0, 0, 0, 0, \
|
|
false, false, ldmaCfgArbSlotsAs1, \
|
|
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
|
|
loopCnt \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* Generic DMA transfer configuration for memory to/from peripheral transfers.
|
|
*/
|
|
#define LDMA_TRANSFER_CFG_PERIPHERAL( signal ) \
|
|
{ \
|
|
signal, 0, 0, 0, 0, \
|
|
false, false, ldmaCfgArbSlotsAs1, \
|
|
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* Generic DMA transfer configuration for looped memory to/from peripheral transfers.
|
|
*/
|
|
#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP( signal, loopCnt ) \
|
|
{ \
|
|
signal, 0, 0, 0, 0, \
|
|
false, false, ldmaCfgArbSlotsAs1, \
|
|
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for single memory to memory word transfer.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of words to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeWord, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for single memory to memory half-word transfer.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of half-words to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeHalf, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for single memory to memory byte transfer.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory word transfer.
|
|
*
|
|
* The link address must be an absolute address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is not
|
|
* initialized.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of words to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeWord, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeAbs, \
|
|
.link = 1, \
|
|
.linkAddr = 0 /* Must be set runtime ! */ \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory half-word transfer.
|
|
*
|
|
* The link address must be an absolute address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is not
|
|
* initialized.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of half-words to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeHalf, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeAbs, \
|
|
.link = 1, \
|
|
.linkAddr = 0 /* Must be set runtime ! */ \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory byte transfer.
|
|
*
|
|
* The link address must be an absolute address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is not
|
|
* initialized.
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeAbs, \
|
|
.link = 1, \
|
|
.linkAddr = 0 /* Must be set runtime ! */ \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory word transfer.
|
|
*
|
|
* The link address is a relative address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is
|
|
* initialized to 4, assuming that the next descriptor immediately follows
|
|
* this descriptor (in memory).
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of words to transfer.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD( src, dest, count, linkjmp ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeWord, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory half-word transfer.
|
|
*
|
|
* The link address is a relative address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is
|
|
* initialized to 4, assuming that the next descriptor immediately follows
|
|
* this descriptor (in memory).
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of half-words to transfer.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF( src, dest, count, linkjmp ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeHalf, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for linked memory to memory byte transfer.
|
|
*
|
|
* The link address is a relative address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is
|
|
* initialized to 4, assuming that the next descriptor immediately follows
|
|
* this descriptor (in memory).
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE( src, dest, count, linkjmp ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 1, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 0, \
|
|
.reqMode = ldmaCtrlReqModeAll, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for byte transfers from a peripheral to memory.
|
|
* @param[in] src Peripheral data source register address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 0, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeBlock, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncNone, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for byte transfers from memory to a peripheral
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Peripheral data register destination address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE( src, dest, count ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 0, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeBlock, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncNone, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for byte transfers from a peripheral to memory.
|
|
* @param[in] src Peripheral data source register address.
|
|
* @param[in] dest Destination data address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE( src, dest, count, linkjmp ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 0, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeBlock, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncNone, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncOne, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for byte transfers from memory to a peripheral
|
|
* @param[in] src Source data address.
|
|
* @param[in] dest Peripheral data register destination address.
|
|
* @param[in] count Number of bytes to transfer.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE( src, dest, count, linkjmp ) \
|
|
{ \
|
|
.xfer = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeXfer, \
|
|
.structReq = 0, \
|
|
.xferCnt = ( count ) - 1, \
|
|
.byteSwap = 0, \
|
|
.blockSize = ldmaCtrlBlockSizeUnit1, \
|
|
.doneIfs = 1, \
|
|
.reqMode = ldmaCtrlReqModeBlock, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = ldmaCtrlSrcIncOne, \
|
|
.size = ldmaCtrlSizeByte, \
|
|
.dstInc = ldmaCtrlDstIncNone, \
|
|
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
|
|
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
|
|
.srcAddr = (uint32_t)(src), \
|
|
.dstAddr = (uint32_t)(dest), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for Immediate WRITE transfer
|
|
* @param[in] value Immediate value to write.
|
|
* @param[in] address Write sddress.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_WRITE( value, address ) \
|
|
{ \
|
|
.wri = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeWrite, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 1, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.immVal = (value), \
|
|
.dstAddr = (uint32_t)(address), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for Immediate WRITE transfer
|
|
*
|
|
* The link address must be an absolute address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is not
|
|
* initialized.
|
|
* @param[in] value Immediate value to write.
|
|
* @param[in] address Write sddress.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKABS_WRITE( value, address ) \
|
|
{ \
|
|
.wri = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeWrite, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 0, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.immVal = (value), \
|
|
.dstAddr = (uint32_t)(address), \
|
|
.linkMode = ldmaLinkModeAbs, \
|
|
.link = 1, \
|
|
.linkAddr = 0 /* Must be set runtime ! */ \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for Immediate WRITE transfer
|
|
* @param[in] value Immediate value to write.
|
|
* @param[in] address Write sddress.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_WRITE( value, address, linkjmp ) \
|
|
{ \
|
|
.wri = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeWrite, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 0, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.immVal = (value), \
|
|
.dstAddr = (uint32_t)(address), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for SYNC transfer
|
|
* @param[in] set Sync pattern bits to set.
|
|
* @param[in] clr Sync pattern bits to clear.
|
|
* @param[in] matchValue Sync pattern to match.
|
|
* @param[in] matchEnable Sync pattern bits to enable for match.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_SINGLE_SYNC( set, clr, matchValue, matchEnable ) \
|
|
{ \
|
|
.sync = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeSync, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 1, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.syncSet = (set), \
|
|
.syncClr = (clr), \
|
|
.matchVal = (matchValue), \
|
|
.matchEn = (matchEnable), \
|
|
.linkMode = 0, \
|
|
.link = 0, \
|
|
.linkAddr = 0 \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for SYNC transfer
|
|
*
|
|
* The link address must be an absolute address.
|
|
* @note
|
|
* The linkAddr member of the transfer descriptor is not
|
|
* initialized.
|
|
* @param[in] set Sync pattern bits to set.
|
|
* @param[in] clr Sync pattern bits to clear.
|
|
* @param[in] matchValue Sync pattern to match.
|
|
* @param[in] matchEnable Sync pattern bits to enable for match.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKABS_SYNC( set, clr, matchValue, matchEnable ) \
|
|
{ \
|
|
.sync = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeSync, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 0, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.syncSet = (set), \
|
|
.syncClr = (clr), \
|
|
.matchVal = (matchValue), \
|
|
.matchEn = (matchEnable), \
|
|
.linkMode = ldmaLinkModeAbs, \
|
|
.link = 1, \
|
|
.linkAddr = 0 /* Must be set runtime ! */ \
|
|
} \
|
|
}
|
|
|
|
/**
|
|
* @brief
|
|
* DMA descriptor initializer for SYNC transfer
|
|
* @param[in] set Sync pattern bits to set.
|
|
* @param[in] clr Sync pattern bits to clear.
|
|
* @param[in] matchValue Sync pattern to match.
|
|
* @param[in] matchEnable Sync pattern bits to enable for match.
|
|
* @param[in] linkjmp Address of descriptor to link to expressed as a
|
|
* signed number of descriptors from "here".
|
|
* 1=one descriptor forward in memory,
|
|
* 0=one this descriptor,
|
|
* -1=one descriptor back in memory.
|
|
*/
|
|
#define LDMA_DESCRIPTOR_LINKREL_SYNC( set, clr, matchValue, matchEnable, linkjmp ) \
|
|
{ \
|
|
.sync = \
|
|
{ \
|
|
.structType = ldmaCtrlStructTypeSync, \
|
|
.structReq = 1, \
|
|
.xferCnt = 0, \
|
|
.byteSwap = 0, \
|
|
.blockSize = 0, \
|
|
.doneIfs = 0, \
|
|
.reqMode = 0, \
|
|
.decLoopCnt = 0, \
|
|
.ignoreSrec = 0, \
|
|
.srcInc = 0, \
|
|
.size = 0, \
|
|
.dstInc = 0, \
|
|
.srcAddrMode = 0, \
|
|
.dstAddrMode = 0, \
|
|
.syncSet = (set), \
|
|
.syncClr = (clr), \
|
|
.matchVal = (matchValue), \
|
|
.matchEn = (matchEnable), \
|
|
.linkMode = ldmaLinkModeRel, \
|
|
.link = 1, \
|
|
.linkAddr = ( linkjmp ) * 4 \
|
|
} \
|
|
}
|
|
|
|
/*******************************************************************************
|
|
***************************** PROTOTYPES **********************************
|
|
******************************************************************************/
|
|
|
|
void LDMA_DeInit( void );
|
|
void LDMA_Init( LDMA_Init_t *init );
|
|
void LDMA_StartTransfer( int ch,
|
|
LDMA_TransferCfg_t *transfer,
|
|
LDMA_Descriptor_t *descriptor );
|
|
void LDMA_StopTransfer( int ch );
|
|
bool LDMA_TransferDone( int ch );
|
|
uint32_t LDMA_TransferRemainingCount( int ch );
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Clear one or more pending LDMA interrupts.
|
|
*
|
|
* @param[in] flags
|
|
* Pending LDMA interrupt sources to clear. Use one or more valid
|
|
* interrupt flags for the LDMA module (LDMA_IFC_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE void LDMA_IntClear(uint32_t flags)
|
|
{
|
|
LDMA->IFC = flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Disable one or more LDMA interrupts.
|
|
*
|
|
* @param[in] flags
|
|
* LDMA interrupt sources to disable. Use one or more valid
|
|
* interrupt flags for the LDMA module (LDMA_IEN_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE void LDMA_IntDisable(uint32_t flags)
|
|
{
|
|
LDMA->IEN &= ~flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Enable one or more LDMA interrupts.
|
|
*
|
|
* @note
|
|
* Depending on the use, a pending interrupt may already be set prior to
|
|
* enabling the interrupt. Consider using LDMA_IntClear() prior to enabling
|
|
* if such a pending interrupt should be ignored.
|
|
*
|
|
* @param[in] flags
|
|
* LDMA interrupt sources to enable. Use one or more valid
|
|
* interrupt flags for the LDMA module (LDMA_IEN_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE void LDMA_IntEnable(uint32_t flags)
|
|
{
|
|
LDMA->IEN |= flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get pending LDMA interrupt flags.
|
|
*
|
|
* @note
|
|
* The event bits are not cleared by the use of this function.
|
|
*
|
|
* @return
|
|
* LDMA interrupt sources pending. Returns one or more valid
|
|
* interrupt flags for the LDMA module (LDMA_IF_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE uint32_t LDMA_IntGet(void)
|
|
{
|
|
return LDMA->IF;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get enabled and pending LDMA interrupt flags.
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* Useful for handling more interrupt sources in the same interrupt handler.
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*
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* @note
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* Interrupt flags are not cleared by the use of this function.
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*
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* @return
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* Pending and enabled LDMA interrupt sources
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|
* The return value is the bitwise AND of
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* - the enabled interrupt sources in LDMA_IEN and
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|
* - the pending interrupt flags LDMA_IF
|
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******************************************************************************/
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__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)
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{
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uint32_t ien;
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|
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ien = LDMA->IEN;
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return LDMA->IF & ien;
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}
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/***************************************************************************//**
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* @brief
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|
* Set one or more pending LDMA interrupts
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|
*
|
|
* @param[in] flags
|
|
* LDMA interrupt sources to set to pending. Use one or more valid
|
|
* interrupt flags for the LDMA module (LDMA_IFS_nnn).
|
|
******************************************************************************/
|
|
__STATIC_INLINE void LDMA_IntSet(uint32_t flags)
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|
{
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|
LDMA->IFS = flags;
|
|
}
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|
|
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/** @} (end addtogroup LDMA) */
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|
/** @} (end addtogroup EM_Library) */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
|
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#endif /* __SILICON_LABS_EM_LDMA_H__ */
|