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Updating F401C to be within bounds of SPI max is 3

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This commit is contained in:
Chris Hamilton 2014-03-27 23:46:26 -07:00
parent a9d00d3350
commit f70cd978bc
2 changed files with 9 additions and 9 deletions
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2
boards/STM32F401CDISCOVERY.py
View File

@ -29,7 +29,7 @@ chip = {
'flash' : 256,
'speed' : 84,
'usart' : 3,
'spi' : 4,
'spi' : 3,
'i2c' : 3,
'adc' : 1,
'dac' : 0,

16
boards/pins/stm32f401.csv
View File

@ -1,9 +1,9 @@
UQFN48,WLCSP49,LQFP64,LQFP100,UFBGA100,Name,Type,IO,Alternate,Additional
0,0,0,1,B2,PE2,I/O,FT,SPI4_SCK/TRACECLK/EVENTOUT,
0,0,0,1,B2,PE2,I/O,FT,TRACECLK/EVENTOUT,
0,0,0,2,A1,PE3,I/O,FT,TRACED0/EVENTOUT,
0,0,0,3,B1,PE4,I/O,FT,SPI4_NSS/TRACED1/EVENTOUT,
0,0,0,4,C2,PE5,I/O,FT,SPI4_MISO/TIM9_CH1/TRACED2/EVENTOUT,
0,0,0,5,D2,PE6,I/O,FT,SPI4_MOSI/TIM9_CH2/TRACED3/EVENTOUT,
0,0,0,3,B1,PE4,I/O,FT,TRACED1/EVENTOUT,
0,0,0,4,C2,PE5,I/O,FT,TIM9_CH1/TRACED2/EVENTOUT,
0,0,0,5,D2,PE6,I/O,FT,TIM9_CH2/TRACED3/EVENTOUT,
0,0,0,0,D3,VSS,S,,,
0,0,0,0,C4,VDD,S, ,,
1,B7,1,6,E2,VBAT,S, ,,
@ -46,10 +46,10 @@ UQFN48,WLCSP49,LQFP64,LQFP100,UFBGA100,Name,Type,IO,Alternate,Additional
0,0,0,39,L7,PE8,I/O,FT,TIM1_CH1N/EVENTOUT,
0,0,0,40,M8,PE9,I/O,FT,TIM1_CH1/EVENTOUT,
0,0,0,41,L8,PE10,I/O,FT,TIM1_CH2N/EVENTOUT,
0,0,0,42,M9,PE11,I/O,FT,SPI4_NSS/TIM1_CH2/EVENTOUT,
0,0,0,43,L9,PE12,I/O,FT,SPI4_SCK/TIM1_CH3N/EVENTOUT,
0,0,0,44,M10,PE13,I/O,FT,SPI4_MISO/TIM1_CH3/EVENTOUT,
0,0,0,45,M11,PE14,I/O,FT,SPI4_MOSI/TIM1_CH4/EVENTOUT,
0,0,0,42,M9,PE11,I/O,FT,TIM1_CH2/EVENTOUT,
0,0,0,43,L9,PE12,I/O,FT,TIM1_CH3N/EVENTOUT,
0,0,0,44,M10,PE13,I/O,FT,TIM1_CH3/EVENTOUT,
0,0,0,45,M11,PE14,I/O,FT,TIM1_CH4/EVENTOUT,
0,0,0,46,M12,PE15,I/O,FT,TIM1_BKIN/EVENTOUT,
21,E3,29,47,L10,PB10,I/O,FT,SPI2_SCK/I2S2_CK/I2C2_SCL/TIM2_CH3/EVENTOUT,
0,0,0,0,K9,PB11,I/O,FT,EVENTOUT,

1 UQFN48 WLCSP49 LQFP64 LQFP100 UFBGA100 Name Type IO Alternate Additional
2 0 0 0 1 B2 PE2 I/O FT SPI4_SCK/TRACECLK/EVENTOUT TRACECLK/EVENTOUT
3 0 0 0 2 A1 PE3 I/O FT TRACED0/EVENTOUT
4 0 0 0 3 B1 PE4 I/O FT SPI4_NSS/TRACED1/EVENTOUT TRACED1/EVENTOUT
5 0 0 0 4 C2 PE5 I/O FT SPI4_MISO/TIM9_CH1/TRACED2/EVENTOUT TIM9_CH1/TRACED2/EVENTOUT
6 0 0 0 5 D2 PE6 I/O FT SPI4_MOSI/TIM9_CH2/TRACED3/EVENTOUT TIM9_CH2/TRACED3/EVENTOUT
7 0 0 0 0 D3 VSS S
8 0 0 0 0 C4 VDD S
9 1 B7 1 6 E2 VBAT S
46 0 0 0 39 L7 PE8 I/O FT TIM1_CH1N/EVENTOUT
47 0 0 0 40 M8 PE9 I/O FT TIM1_CH1/EVENTOUT
48 0 0 0 41 L8 PE10 I/O FT TIM1_CH2N/EVENTOUT
49 0 0 0 42 M9 PE11 I/O FT SPI4_NSS/TIM1_CH2/EVENTOUT TIM1_CH2/EVENTOUT
50 0 0 0 43 L9 PE12 I/O FT SPI4_SCK/TIM1_CH3N/EVENTOUT TIM1_CH3N/EVENTOUT
51 0 0 0 44 M10 PE13 I/O FT SPI4_MISO/TIM1_CH3/EVENTOUT TIM1_CH3/EVENTOUT
52 0 0 0 45 M11 PE14 I/O FT SPI4_MOSI/TIM1_CH4/EVENTOUT TIM1_CH4/EVENTOUT
53 0 0 0 46 M12 PE15 I/O FT TIM1_BKIN/EVENTOUT
54 21 E3 29 47 L10 PB10 I/O FT SPI2_SCK/I2S2_CK/I2C2_SCL/TIM2_CH3/EVENTOUT
55 0 0 0 0 K9 PB11 I/O FT EVENTOUT