mirror of
https://github.com/espruino/Espruino.git
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Merge branch 'master' of https://github.com/etx/Espruino into etx-master
Tweaks for new build system and to remove Nucleo-specific USB define
This commit is contained in:
Gordon Williams
commit
a277d8c412
134
boards/NUCLEOF413ZH.py
Normal file
134
boards/NUCLEOF413ZH.py
Normal file
@ -0,0 +1,134 @@
|
||||
#!/bin/false
|
||||
# -*- coding: utf8 -*-
|
||||
# This file is part of Espruino, a JavaScript interpreter for Microcontrollers
|
||||
#
|
||||
# Copyright (C) 2013 Gordon Williams <gw@pur3.co.uk>
|
||||
# Copyright (C) 2014 Alain Sézille for NucleoF411RE specific lines of this file
|
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#
|
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# This Source Code Form is subject to the terms of the Mozilla Public
|
||||
# License, v. 2.0. If a copy of the MPL was not distributed with this
|
||||
# file, You can obtain one at http://mozilla.org/MPL/2.0/.
|
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#
|
||||
# ----------------------------------------------------------------------------------------
|
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# This file contains information for a specific board - the available pins, and where LEDs,
|
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# Buttons, and other in-built peripherals are. It is used to build documentation as well
|
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# as various source and header files for Espruino.
|
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# ----------------------------------------------------------------------------------------
|
||||
|
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import pinutils;
|
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info = {
|
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'name' : "ST NUCLEO-F413ZH",
|
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'link' : [ "http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320"],
|
||||
'default_console' : "EV_SERIAL3", # USART3 by default, the Nucleo's USB is actually running on this too
|
||||
'default_console_tx' : "D8", # USART2_TX on PD8,
|
||||
'default_console_rx' : "D9", # USART2_RX on PD9
|
||||
'variables' : 7423, # (128-12)*1024/16-1
|
||||
'binary_name' : 'espruino_%v_nucleof413zh.bin',
|
||||
'build' : {
|
||||
'optimizeflags' : '-O3 -w',
|
||||
'libraries' : [
|
||||
'USB_HID',
|
||||
'NET',
|
||||
'GRAPHICS',
|
||||
'NEOPIXEL'
|
||||
],
|
||||
'makefile' : [
|
||||
'NUCLEO=1',
|
||||
'DEFINES+=-DUSE_USB_OTG_FS=1 -DUSB_NO_VBUS_SENSE=1',
|
||||
'STLIB=STM32F413xH',
|
||||
'PRECOMPILED_OBJS+=$(ROOT)/targetlibs/stm32f4/lib/startup_stm32f413xx.o'
|
||||
]
|
||||
}
|
||||
};
|
||||
chip = {
|
||||
'part' : "STM32F411RET6",
|
||||
'family' : "STM32F4",
|
||||
'package' : "LQFP144",
|
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'ram' : 320, # 0x0001 8000 long, from 0x2000 0000 to 0x2001 7FFF
|
||||
'flash' : 1536, # 0x0008 0000 long, from 0x0800 0000 to 0x0807 FFFF
|
||||
'speed' : 100,
|
||||
'usart' : 6,
|
||||
'spi' : 4,
|
||||
'i2c' : 3,
|
||||
'adc' : 1,
|
||||
'dac' : 0,
|
||||
'saved_code' : {
|
||||
# code size 225248 = 0x36FE0 starts at 0x0800 0000 ends at 0x0803 6FE0
|
||||
# so we have some left room for Espruino firmware and no risk to clear it while saving
|
||||
'address' : 0x08060000, # flash_saved_code_start 0x0806 0000 to 0x807 5000
|
||||
# we have enough flash space in this single flash page to save all of the ram
|
||||
'page_size' : 131072, # size of pages : on STM32F411, last 2 pages are 128 Kbytes
|
||||
# we use the last flash page only, furthermore it persists after a firmware flash of the board
|
||||
'pages' : 1, # count of pages we're using to save RAM to Flash,
|
||||
'flash_available' : 512 # binary will have a hole in it, so we just want to test against full size
|
||||
},
|
||||
#'place_text_section' : 0x08010000, # note flash_available above # TODO USELESS
|
||||
};
|
||||
|
||||
devices = {
|
||||
'OSC' : { 'pin_1' : 'H0', # MCO from ST-LINK fixed at 8 Mhz, boards rev MB1136 C-02
|
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'pin_2' : 'H1' },
|
||||
'OSC_RTC' : { 'pin_1' : 'C14', # MB1136 C-02 corresponds to a board configured with on-board 32kHz oscillator
|
||||
'pin_2' : 'C15' },
|
||||
'LED1' : { 'pin' : 'B0'},
|
||||
'LED2' : { 'pin' : 'B14'},
|
||||
'LED3' : { 'pin' : 'B7'},
|
||||
'BTN1' : { 'pin' : 'C13',
|
||||
'inverted' : False, # 1 when unpressed, 0 when pressed! (Espruino board is 1 when pressed)
|
||||
'pinstate': 'IN_PULLUP', # to specify INPUT, OUPUT PULL_UP PULL_DOWN..
|
||||
},
|
||||
'JTAG' : {
|
||||
'pin_MS' : 'A13',
|
||||
'pin_CK' : 'A14',
|
||||
'pin_DI' : 'A15'
|
||||
},
|
||||
'USB' : { #'pin_otg_pwr' : 'C0',
|
||||
#'pin_vsense' : 'A9',
|
||||
'pin_dm' : 'A11',
|
||||
'pin_dp' : 'A12',
|
||||
#'pin_vbus' : 'A9',
|
||||
'pin_id' : 'A10', },
|
||||
'NUCLEO_A' : [ 'A0','A1','A4','B0','C1','C0' ],
|
||||
'NUCLEO_D' : [ 'A3','A2','A10','B3','B5','B4','B10','A8','A9','C7','B6','A7','A6','A5','B9','B8' ],
|
||||
};
|
||||
|
||||
# left-right, or top-bottom order
|
||||
board = {
|
||||
'left' : [ 'C10', 'C12', 'VDD', 'BOOT0', 'NC', 'NC', 'A13', 'A14', 'A15', 'GND', 'B7', 'C13', 'C14', 'C15', 'H0', 'H1', 'VBAT', 'C2', 'C3'],
|
||||
'left2' : [ 'C11', 'D2', 'E5V', 'GND', 'NC', 'IOREF', 'RESET', '3V3', '5V', 'GND', 'GND', 'VIN', 'NC', 'A0', 'A1', 'A4', 'B0', 'C1', 'C0'],
|
||||
'right2' : [ 'C9', 'B8', 'B9', 'AVDD', 'GND', 'A5', 'A6', 'A7', 'B6','C7','A9','A8','B10','B4','B5','B3','A10','A2','A3'],
|
||||
'right' : [ 'C8', 'C6', 'C5', 'U5V', 'NC', 'A12', 'A11', 'B12', 'NC', 'GND', 'B2', 'B1', 'B15', 'B14', 'B13', 'AGND', 'C4', 'NC', 'NC'],
|
||||
};
|
||||
board["_css"] = """
|
||||
#board {
|
||||
width: 713px;
|
||||
height: 800px;
|
||||
left: 200px;
|
||||
background-image: url(img/NUCLEOF411RE.jpg);
|
||||
}
|
||||
#boardcontainer {
|
||||
height: 1020px;
|
||||
}
|
||||
#left {
|
||||
top: 310px;
|
||||
right: 640px;
|
||||
}
|
||||
#left2 {
|
||||
top: 310px;
|
||||
left: 85px;
|
||||
}
|
||||
|
||||
#right {
|
||||
top: 310px;
|
||||
left: 615px;
|
||||
}
|
||||
#right2 {
|
||||
top: 310px;
|
||||
right: 105px;
|
||||
}
|
||||
""";
|
||||
|
||||
def get_pins():
|
||||
pins = pinutils.scan_pin_file([], 'stm32f413.csv', 6, 9, 10)
|
||||
pins = pinutils.scan_pin_af_file(pins, 'stm32f413_af.csv', 0, 1)
|
||||
return pinutils.only_from_package(pinutils.fill_gaps_in_pin_list(pins), chip["package"])
|
||||
110
boards/pins/stm32f413.csv
Normal file
110
boards/pins/stm32f413.csv
Normal file
@ -0,0 +1,110 @@
|
||||
UQFN48,WLCSP49,LQFP64,LQFP100,UFBGA100,LQFP144,Name,Type,IO,Alternate,Additional
|
||||
0,0,0,1,B2,1,PE2,I/O,FT,TRACECLK/EVENTOUT,
|
||||
0,0,0,2,A1,2,PE3,I/O,FT,TRACED0/EVENTOUT,
|
||||
0,0,0,3,B1,3,PE4,I/O,FT,TRACED1/EVENTOUT,
|
||||
0,0,0,4,C2,4,PE5,I/O,FT,TIM9_CH1/TRACED2/EVENTOUT,
|
||||
0,0,0,5,D2,5,PE6,I/O,FT,TIM9_CH2/TRACED3/EVENTOUT,
|
||||
0,0,0,0,D3,0,VSS,S,,,
|
||||
0,0,0,0,C4,0,VDD,S, ,,
|
||||
1,B7,1,6,E2,6,VBAT,S, ,,
|
||||
2,D5,2,7,C1,7,PC13-ANTI_TAMP,I/O,FT,EVENTOUT,RTC_TAMP1/RTC_OUT/RTC_TS
|
||||
3,C7,3,8,D1,8,PC14-OSC32_IN(PC14),I/O,FT,EVENTOUT,OSC32_IN
|
||||
4,0,4,9,E1,9,PC15-OSC32_OUT(PC15),I/O,FT,EVENTOUT,OSC32_OUT
|
||||
0,0,0,10,F2,0,VSS,S,,,
|
||||
0,0,0,11,G2,0,VDD,S,,,
|
||||
5,D7,5,12,F1,23,PH0-OSC_IN(PH0),I/O,FT,EVENTOUT,OSC_IN
|
||||
6,D6,6,13,G1,24,PH1-OSC_OUT(PH1),I/O,FT,EVENTOUT,OSC_OUT
|
||||
7,E7,7,14,H2,25,NRST,I/O,RST,EVENTOUT,
|
||||
0,0,8,15,H1,26,PC0,I/O,FT,EVENTOUT,ADC1_IN10
|
||||
0,0,9,16,J2,27,PC1,I/O,FT,EVENTOUT,ADC1_IN11
|
||||
0,0,10,17,J3,28,PC2,I/O,FT,SPI2_MISO/I2S2ext_SD/EVENTOUT,ADC1_IN12
|
||||
0,0,11,18,K2,29,PC3,I/O,FT,SPI2_MOSI/I2S2_SD/EVENTOUT,ADC1_IN13
|
||||
0,0,0,19,0,0,VDD,S,,,
|
||||
8,E6,12,20,0,0,VSSA-VREF-,S,,,
|
||||
0,0,0,0,J11,0,VSSA,S,,,
|
||||
0,0,0,0,K1,0,VREF-,S,,,
|
||||
9,0,13,0,0,0,VDDA-VREF+,S,,,
|
||||
0,0,0,21,L1,0,VREF+,S,,,
|
||||
0,F7,0,22,M1,0,VDDA,S,,,
|
||||
10,F6,14,23,L2,34,PA0-WKUP(PA0),I/O,FT,USART2_CTS/TIM2_CH1/TIM2_ETR/TIM5_CH1/EVENTOUT,ADC1_IN0/WKUP
|
||||
11,G7,15,24,M2,35,PA1,I/O,FT,USART2_RTS/TIM2_CH2/TIM5_CH2/EVENTOUT,ADC1_IN1
|
||||
12,E5,16,25,K3,36,PA2,I/O,FT,USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/EVENTOUT,ADC1_IN2
|
||||
13,E4,17,26,L3,37,PA3,I/O,FT,USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/EVENTOUT,ADC1_IN3
|
||||
0,0,18,27,0,38,VSS,S,,,
|
||||
0,0,19,28,0,39,VDD,S,,,
|
||||
0,0,0,0,E3,0,BYPASS_REG,I,FT,,
|
||||
14,G6,20,29,M3,40,PA4,I/O,FT,SPI1_NSS/SPI3_NSS/USART2_CK/I2S3_WS/EVENTOUT,ADC1_IN4
|
||||
15,F5,21,30,K4,41,PA5,I/O,FT,SPI1_SCK/TIM2_CH1/TIM2_ETR/EVENTOUT,ADC1_IN5
|
||||
16,F4,22,31,L4,42,PA6,I/O,FT,SPI1_MISO/TIM3_CH1/TIM1_BKIN/EVENTOUT,ADC1_IN6
|
||||
17,F3,23,32,M4,43,PA7,I/O,FT,SPI1_MOSI/TIM3_CH2/TIM1_CH1N/EVENTOUT,ADC1_IN7
|
||||
0,0,24,33,K5,44,PC4,I/O,FT,EVENTOUT,ADC1_IN14
|
||||
0,0,25,34,L5,45,PC5,I/O,FT,EVENTOUT,ADC1_IN15
|
||||
18,G5,26,35,M5,46,PB0,I/O,FT,TIM3_CH3/TIM1_CH2N/EVENTOUT,ADC1_IN8
|
||||
19,G4,27,36,M6,47,PB1,I/O,FT,TIM3_CH4/TIM1_CH3N/EVENTOUT,ADC1_IN9
|
||||
20,G3,28,37,L6,48,PB2-BOOT1(PB2),I/O,FT,EVENTOUT,
|
||||
0,0,0,38,M7,58,PE7,I/O,FT,TIM1_ETR/EVENTOUT,
|
||||
0,0,0,39,L7,59,PE8,I/O,FT,TIM1_CH1N/EVENTOUT,
|
||||
0,0,0,40,M8,60,PE9,I/O,FT,TIM1_CH1/EVENTOUT,
|
||||
0,0,0,41,L8,63,PE10,I/O,FT,TIM1_CH2N/EVENTOUT,
|
||||
0,0,0,42,M9,64,PE11,I/O,FT,TIM1_CH2/EVENTOUT,
|
||||
0,0,0,43,L9,65,PE12,I/O,FT,TIM1_CH3N/EVENTOUT,
|
||||
0,0,0,44,M10,66,PE13,I/O,FT,TIM1_CH3/EVENTOUT,
|
||||
0,0,0,45,M11,67,PE14,I/O,FT,TIM1_CH4/EVENTOUT,
|
||||
0,0,0,46,M12,68,PE15,I/O,FT,TIM1_BKIN/EVENTOUT,
|
||||
21,E3,29,47,L10,69,PB10,I/O,FT,SPI2_SCK/I2S2_CK/I2C2_SCL/TIM2_CH3/EVENTOUT,
|
||||
0,0,0,0,K9,70,PB11,I/O,FT,EVENTOUT,
|
||||
22,G2,30,48,L11,71,VCAP_1,S,,,
|
||||
23,D3,31,49,F12,0,VSS,S,,,
|
||||
24,F2,32,50,G12,72,VDD,S,,,
|
||||
25,E2,33,51,L12,73,PB12,I/O,FT,SPI2_NSS/I2S2_WS/I2C2_SMBA/TIM1_BKIN/EVENTOUT,
|
||||
26,G1,34,52,K12,74,PB13,I/O,FT,SPI2_SCK/I2S2_CK/TIM1_CH1N/EVENTOUT,
|
||||
27,F1,35,53,K11,75,PB14,I/O,FT,SPI2_MISO/TIM1_CH2N/I2S2ext_SD/EVENTOUT,
|
||||
28,E1,36,54,K10,76,PB15,I/O,FT,SPI2_MOSI/I2S2_SD/TIM1_CH3N/EVENTOUT,RTC_REFIN
|
||||
0,0,77,55,0,77,PD8,I/O,FT,EVENTOUT,
|
||||
0,0,78,56,K8,78,PD9,I/O,FT,EVENTOUT,
|
||||
0,0,0,57,J12,79,PD10,I/O,FT,EVENTOUT,
|
||||
0,0,0,58,J11,80,PD11,I/O,FT,EVENTOUT,
|
||||
0,0,0,59,J10,81,PD12,I/O,FT,TIM4_CH1/EVENTOUT,
|
||||
0,0,0,60,H12,82,PD13,I/O,FT,TIM4_CH2/EVENTOUT,
|
||||
0,0,0,61,H11,85,PD14,I/O,FT,TIM4_CH3/EVENTOUT,
|
||||
0,0,0,62,H10,86,PD15,I/O,FT,TIM4_CH4/EVENTOUT,
|
||||
0,0,37,63,E12,96,PC6,I/O,FT,I2S2_MCK/SDIO_D6/USART6_TX/TIM3_CH1/EVENTOUT,
|
||||
0,0,38,64,E11,97,PC7,I/O,FT,I2S3_MCK/SDIO_D7/USART6_RX/TIM3_CH2/EVENTOUT,
|
||||
0,0,39,65,E10,98,PC8,I/O,FT,SDIO_D0/TIM3_CH3/USART6_CK/EVENTOUT,
|
||||
0,0,40,66,D12,99,PC9,I/O,FT,I2S_CKIN/MCO_2/SDIO_D1/I2C3_SDA/TIM3_CH4/EVENTOUT,
|
||||
29,D1,41,67,D11,100,PA8,I/O,FT,MCO+1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT,
|
||||
30,D2,42,68,D10,101,PA9,I/O,FT,USART1_TX/TIM1_CH2/I2C3_SMBA/EVENTOUT,OTG_FS_VBUS
|
||||
31,C2,43,69,C12,102,PA10,I/O,FT,USART1_RX/TIM1_CH3/OTG_FS_ID/EVENTOUT,
|
||||
32,C1,44,70,B12,103,PA11,I/O,FT,USART1_CTS/USART6_TX/TIM1_CH4/OTG_FS_DM/EVENTOUT,
|
||||
33,C3,45,71,A12,104,PA12,I/O,FT,USART1_RTS/USART6_RX/TIM1_ETR/OTG_FS_DP/EVENTOUT,
|
||||
34,B3,46,72,A11,105,PA13(JTMS-SWDIO),I/O,FT,JTMS-SWDIO/EVENTOUT,
|
||||
0,0,0,73,C11,106,VCAP_2,S,,,
|
||||
35,B1,47,74,F11,107,VSS,S,,,
|
||||
36,,48,75,G11,0,VDD,S,,,
|
||||
0,B2,0,0,0,108,VDD,S,,,
|
||||
37,A1,49,76,A10,109,PA14(JTCK-SWCLK),I/O,FT,JTCK-SWCLK/EVENTOUT,
|
||||
38,A2,50,77,A9,110,PA15(JTDI),I/O,FT,JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1/TIM2_ETR/SPI1_NSS/EVENTOUT,
|
||||
0,0,51,78,B11,111,PC10,I/O,FT,SPI3_SCK/I2S3_CK/SDIO_D2/EVENTOUT,
|
||||
0,0,52,79,C10,112,PC11,I/O,FT,SPI3_MISO/SDIO_D3/I2S3ext_SD/EVENTOUT,
|
||||
0,0,53,80,B10,113,PC12,I/O,FT,SDIO_CK/SPI3_MOSI/I2S3_SD/EVENTOUT,
|
||||
0,0,0,81,C9,114,PD0,I/O,FT,EVENTOUT,
|
||||
0,0,0,82,B9,115,PD1,I/O,FT,EVENTOUT,
|
||||
0,0,54,83,C8,116,PD2,I/O,FT,TIM3_ETR/SDIO_CMD/EVENTOUT,
|
||||
0,0,0,84,B8,117,PD3,I/O,FT,SPI2_SCK/I2S2_CK/USART2_CTS/EVENTOUT,
|
||||
0,0,0,85,B7,118,PD4,I/O,FT,USART2_RTS/EVENTOUT,
|
||||
0,0,0,86,A6,119,PD5,I/O,FT,USART2_TX/EVENTOUT,
|
||||
0,0,0,87,B6,122,PD6,I/O,FT,USART2_RX/EVENTOUT,
|
||||
0,0,0,88,A5,123,PD7,I/O,FT,USART2_CK/EVENTOUT,
|
||||
39,A3,55,89,A8,133,PB3(JTDO-TRACESWO),I/O,FT,JTDO-SWO/SPI3_SCK/I2S3_CK/I2C2_SDA/TIM2_CH2/SPI1_SCK/EVENTOUT,
|
||||
40,A4,56,90,A7,134,PB4(NJTRST),I/O,FT,NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2C3_SDA/I2S3ext_SD/EVENTOUT,
|
||||
41,B4,57,91,C5,135,PB5,I/O,FT,I2C1_SMBA/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/I2S3_SD/EVENTOUT,
|
||||
42,C4,58,92,B5,136,PB6,I/O,FT,I2C1_SCL/TIM4_CH1/USART1_TX/EVENTOUT,
|
||||
43,D4,59,93,B4,137,PB7,I/O,FT,I2C1_SDA/USART1_RX/TIM4_CH2/EVENTOUT,
|
||||
44,A5,60,94,A4,138,BOOT0,I,B,,VPP
|
||||
45,B5,61,95,A3,139,PB8,I/O,FT,TIM4_CH3/SDIO_D4/TIM10_CH1/I2C1_SCL/EVENTOUT,
|
||||
46,C5,62,96,B3,140,PB9,I/O,FT,SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/I2C1_SDA/EVENTOUT,
|
||||
0,0,0,97,C3,141,PE0,I/O,FT,TIM4_ETR/EVENTOUT,
|
||||
0,0,0,98,A2,142,PE1,I/O,FT,EVENTOUT,
|
||||
47,A6,63,99,H3,0,VSS,S,,,
|
||||
0,B6,0,0,0,143,PDR_ON,I,FT,,
|
||||
48,A7,64,100,0,144,VDD,S,,,
|
||||
|
82
boards/pins/stm32f413_af.csv
Normal file
82
boards/pins/stm32f413_af.csv
Normal file
@ -0,0 +1,82 @@
|
||||
,AF00,AF01,AF02,AF03,AF04,AF05,AF06,AF07,AF08,AF09,AF10,AF11,AF12,AF13,AF14,AF15
|
||||
PA0,-,TIM2_CH1/TIM2_ETR,TIM5_CH1,-,-,-,-,USART2_CTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA1,-,TIM2_CH2,TIM5_CH2,-,-,-,-,USART2_RTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA2,-,TIM2_CH3,TIM5_CH3,TIM9_CH1,-,-,-,USART2_TX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA3,-,TIM2_CH4,TIM5_CH4,TIM9_CH2,-,-,-,USART2_RX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA4,-,-,-,-,-,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA5,-,TIM2_CH1/TIM2_ETR,-,-,-,SPI1_SCK,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA6,-,TIM1_BKIN,TIM3_CH1,-,-,SPI1_MISO,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA7,-,TIM1_CH1N,TIM3_CH2,-,-,SPI1_MOSI,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA8,MCO_1,TIM1_CH1,-,-,I2C3_SCL,-,-,USART1_CK,-,-,OTG_FS_SOF,-,-,-,-,EVENT OUT
|
||||
PA9,-,TIM1_CH2,-,-,I2C3_SMBA,-,-,USART1_TX,-,-,OTG_FS_VBUS,-,-,-,-,EVENT OUT
|
||||
PA10,-,TIM1_CH3,-,-,-,-,-,USART1_RX,-,-,OTG_FS_ID,-,-,-,-,EVENT OUT
|
||||
PA11,-,TIM1_CH4,-,-,-,-,-,USART1_CTS,USART6_TX,-,OTG_FS_DM,-,-,-,-,EVENT OUT
|
||||
PA12,-,TIM1_ETR,-,-,-,-,-,USART1_RTS,USART6_RX,-,OTG_FS_DP,-,-,-,-,EVENT OUT
|
||||
PA13,JTMS_SWDIO,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA14,JTCK_SWCLK,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PA15,JTDI,TIM2_CH1/TIM2_ETR,-,-,-,SPI1_NSS,SPI3_NSS/I2S3_WS,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB0,-,TIM1_CH2N,TIM3_CH3,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB1,-,TIM1_CH3N,TIM3_CH4,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB2,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB3,JTDO-SWO,TIM2_CH2,-,-,-,SPI1_SCK,SPI3_SCK/I2S3_CK,-,-,I2C2_SDA,-,-,-,-,-,EVENT OUT
|
||||
PB4,JTRST,-,TIM3_CH1,-,-,SPI1_MISO,SPI3_MISO,I2S3ext_SD,-,I2C3_SDA,-,-,-,-,-,EVENT OUT
|
||||
PB5,-,-,TIM3_CH2,-,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB6,-,-,TIM4_CH1,-,I2C1_SCL,-,-,USART1_TX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB7,-,-,TIM4_CH2,-,I2C1_SDA,-,-,USART1_RX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB8,-,-,TIM4_CH3,TIM10_CH1,I2C1_SCL,-,-,-,-,-,-,-,SDIO_D4,-,-,EVENT OUT
|
||||
PB9,-,-,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,-,-,-,-,-,-,SDIO_D5,-,-,EVENT OUT
|
||||
PB10,-,TIM2_CH3,-,-,I2C2_SCL,SPI2_SCK/I2S2_CK,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB12,-,TIM1_BKIN,-,-,I2C2_SMBA,SPI2_NSS/I2S2_WS,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB13,-,TIM1_CH1N,-,-,-,SPI2_SCK/I2S2_CK,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB14,-,TIM1_CH2N,-,-,-,SPI2_MISO,I2S2ext_SD,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PB15,RTC_REFIN,TIM1_CH3N,-,-,-,SPI2_MOSI/I2S2_SD,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC2,-,-,-,-,-,SPI2_MISO,I2S2ext_SD,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC3,-,-,-,-,-,SPI2_MOSI/I2S2_SD,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC4,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC5,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC6,-,-,TIM3_CH1,-,-,I2S2_MCK,-,-,USART6_TX,-,-,-,SDIO_D6,-,-,EVENT OUT
|
||||
PC7,-,-,TIM3_CH2,-,-,-,I2S3_MCK,-,USART6_RX,-,-,-,SDIO_D7,-,-,EVENT OUT
|
||||
PC8,-,-,TIM3_CH3,-,-,-,-,-,USART6_CK,-,-,-,SDIO_D0,-,-,EVENT OUT
|
||||
PC9,MCO_2,-,TIM3_CH4,-,I2C3_SDA,I2S_CKIN,-,-,-,-,-,-,SDIO_D1,-,-,EVENT OUT
|
||||
PC10,-,-,-,-,-,-,SPI3_SCK/I2S3_CK,-,-,-,-,-,SDIO_D2,-,-,EVENT OUT
|
||||
PC11,-,-,-,-,-,I2S3ext_SD,SPI3_MISO,-,-,-,-,-,SDIO_D3,-,-,EVENT OUT
|
||||
PC12,-,-,-,-,-,-,SPI3_MOSI/I2S3_SD,-,-,-,-,-,SDIO_CK,-,-,EVENT OUT
|
||||
PC13,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC14,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PC15,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD2,-,-,TIM3_ETR,-,-,-,-,-,-,-,-,-,SDIO_CMD,-,-,EVENT OUT
|
||||
PD3,-,-,-,-,-,SPI2_SCK/I2S2_CK,-,USART2_CTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD4,-,-,-,-,-,-,-,USART2_RTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD5,-,-,-,-,-,-,-,USART2_TX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD6,-,-,-,-,-,SPI3_MOSI/I2S3_SD,-,USART2_RX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD7,-,-,-,-,-,-,-,USART2_CK,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD8,-,-,-,-,-,-,-,USART3_TX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD9,-,-,-,-,-,-,-,USART3_RX,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD10,-,-,-,-,-,-,-,USART3_CK,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD11,-,-,-,-,-,-,-,USART3_CTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD12,-,-,TIM4_CH1,-,-,-,-,USART3_RTS,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD13,-,-,TIM4_CH2,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD14,-,-,TIM4_CH3,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PD15,-,-,TIM4_CH4,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE0,-,-,TIM4_ETR,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE1,-,TIM1_CH2N,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE2,TRACECLK,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE3,TRACED0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE4,TRACED1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE5,TRACED2,-,-,TIM9_CH1,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE6,TRACED3,-,-,TIM9_CH2,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE7,-,TIM1_ETR,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE8,-,TIM1_CH1N,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE9,-,TIM1_CH1,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE10,-,TIM1_CH2N,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE11,-,TIM1_CH2,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE12,-,TIM1_CH3N,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE13,-,TIM1_CH3,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE14,-,TIM1_CH4,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PE15,-,TIM1_BKIN,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PH0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
PH1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,EVENT OUT
|
||||
|
571
targetlibs/stm32f4/lib/startup_stm32f413xx.s
Executable file
571
targetlibs/stm32f4/lib/startup_stm32f413xx.s
Executable file
@ -0,0 +1,571 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f4013.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.0
|
||||
* @date 08-November-2013
|
||||
* @brief STM32F401xx Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6, DAC1 and DAC2 */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word CAN3_TX_IRQHandler /* CAN3 TX */
|
||||
.word CAN3_RX0_IRQHandler /* CAN3 RX0 */
|
||||
.word CAN3_RX1_IRQHandler /* CAN3 RX1 */
|
||||
.word CAN3_SCE_IRQHandler /* CAN3 SCE */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word 0 /* Reserved */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word UART9_IRQHandler /* UART9 */
|
||||
.word UART10_IRQHandler /* UART10 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word QUADSPI_IRQHandler /* QuadSPI */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */
|
||||
.word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word DFSDM2_FLT0_IRQHandler /* DFSDM2 Filter0 */
|
||||
.word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */
|
||||
.word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */
|
||||
.word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_TX_IRQHandler
|
||||
.thumb_set CAN3_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_RX0_IRQHandler
|
||||
.thumb_set CAN3_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_RX1_IRQHandler
|
||||
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN3_SCE_IRQHandler
|
||||
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART9_IRQHandler
|
||||
.thumb_set UART9_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART10_IRQHandler
|
||||
.thumb_set UART10_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMPI2C1_EV_IRQHandler
|
||||
.thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMPI2C1_ER_IRQHandler
|
||||
.thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM2_FLT0_IRQHandler
|
||||
.thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM2_FLT1_IRQHandler
|
||||
.thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM2_FLT2_IRQHandler
|
||||
.thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM2_FLT3_IRQHandler
|
||||
.thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
4788
targetlibs/stm32f4/lib/stm32f413xx.h
Executable file
4788
targetlibs/stm32f4/lib/stm32f413xx.h
Executable file
File diff suppressed because it is too large
Load Diff
@ -171,6 +171,10 @@
|
||||
#elif defined(STM32F411xE)
|
||||
#define STM32F411xx
|
||||
#include "stm32f411xe.h"
|
||||
#elif defined(STM32F413xH)
|
||||
// #define STM32F411xx
|
||||
#define STM32F401xx
|
||||
#include "stm32f413xx.h"
|
||||
#elif defined(STM32F446xx)
|
||||
#include "stm32f446xx.h"
|
||||
#else
|
||||
|
||||
@ -251,9 +251,9 @@
|
||||
|
||||
/************************* PLL Parameters *************************************/
|
||||
|
||||
// PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
// USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ <-- should be 48Mhz
|
||||
// SYSCLK = PLL_VCO / PLL_P
|
||||
// PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
// USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ <-- should be 48Mhz
|
||||
// SYSCLK = PLL_VCO / PLL_P
|
||||
|
||||
#define PLL_M 8
|
||||
#define PLL_Q 7
|
||||
@ -273,7 +273,14 @@
|
||||
#define PLL_P 4
|
||||
#endif /* STM32F401xx */
|
||||
|
||||
#if defined (STM32F411xx) // 96Mhz
|
||||
#if defined (STM32F411xx) // 100Mhz
|
||||
#undef PLL_Q
|
||||
#define PLL_N 384
|
||||
#define PLL_P 4
|
||||
#define PLL_Q 8
|
||||
#endif /* STM32F411xx */
|
||||
|
||||
#if defined (STM32F413xx) // 100Mhz
|
||||
#undef PLL_Q
|
||||
#define PLL_N 384
|
||||
#define PLL_P 4
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file : usbd_conf.c
|
||||
* @date : 19/05/2015 14:02:19
|
||||
* @date : 19/05/2015 14:02:19
|
||||
* @version : v1.0_Cube
|
||||
* @brief : This file implements the board support package for the USB device library
|
||||
******************************************************************************
|
||||
@ -69,11 +69,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; // __USB_OTG_FS_CLK_ENABLE();
|
||||
|
||||
|
||||
/**USB_OTG_FS GPIO Configuration
|
||||
|
||||
/**USB_OTG_FS GPIO Configuration
|
||||
PA9 ------> USB_OTG_FS_VBUS
|
||||
PA11 ------> USB_OTG_FS_DM
|
||||
PA12 ------> USB_OTG_FS_DP
|
||||
PA12 ------> USB_OTG_FS_DP
|
||||
*/
|
||||
|
||||
/* Configure DM DP Pins */
|
||||
@ -208,27 +208,27 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
{
|
||||
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
|
||||
|
||||
/*Set USB Current Speed*/
|
||||
switch (hpcd->Init.speed)
|
||||
{
|
||||
#ifndef STM32F1
|
||||
#ifndef STM32F1
|
||||
case PCD_SPEED_HIGH:
|
||||
speed = USBD_SPEED_HIGH;
|
||||
break;
|
||||
#endif
|
||||
#endif
|
||||
case PCD_SPEED_FULL:
|
||||
speed = USBD_SPEED_FULL;
|
||||
speed = USBD_SPEED_FULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
speed = USBD_SPEED_FULL;
|
||||
break;
|
||||
speed = USBD_SPEED_FULL;
|
||||
break;
|
||||
}
|
||||
USBD_LL_SetSpeed(hpcd->pData, speed);
|
||||
|
||||
USBD_LL_SetSpeed(hpcd->pData, speed);
|
||||
|
||||
/*Reset Device*/
|
||||
USBD_LL_Reset(hpcd->pData);
|
||||
}
|
||||
@ -243,9 +243,9 @@ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
/* Inform USB library that core enters in suspend Mode */
|
||||
USBD_LL_Suspend(hpcd->pData);
|
||||
#ifndef STM32F1
|
||||
#ifndef STM32F1
|
||||
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
||||
#endif
|
||||
#endif
|
||||
/*Enter in STOP mode */
|
||||
/* USER CODE BEGIN 2 */
|
||||
if (hpcd->Init.low_power_enable)
|
||||
@ -321,11 +321,11 @@ void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
|
||||
{
|
||||
{
|
||||
/* Init USB_IP */
|
||||
/* Link The driver to the stack */
|
||||
/* Link The driver to the stack */
|
||||
hpcd_USB_OTG_FS.pData = pdev;
|
||||
pdev->pData = &hpcd_USB_OTG_FS;
|
||||
pdev->pData = &hpcd_USB_OTG_FS;
|
||||
#ifdef STM32F4
|
||||
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
||||
hpcd_USB_OTG_FS.Init.dev_endpoints = 4;
|
||||
@ -336,7 +336,11 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
|
||||
hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
|
||||
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
||||
#ifdef USB_NO_VBUS_SENSE
|
||||
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
||||
#else
|
||||
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE;
|
||||
#endif
|
||||
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
||||
HAL_PCD_Init(&hpcd_USB_OTG_FS);
|
||||
|
||||
@ -346,7 +350,7 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // HID IN
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x20); // CDC CMD
|
||||
HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // CDC IN
|
||||
#endif
|
||||
#endif
|
||||
#ifdef STM32F1
|
||||
hpcd_USB_OTG_FS.Instance = USB;
|
||||
hpcd_USB_OTG_FS.Init.dev_endpoints = 8;
|
||||
@ -374,7 +378,7 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
|
||||
HAL_PCDEx_PMAConfig(pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); // CDC OUT
|
||||
HAL_PCDEx_PMAConfig(pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); // CDC CMD
|
||||
|
||||
#endif
|
||||
#endif
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
@ -386,18 +390,18 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
|
||||
USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev)
|
||||
{
|
||||
HAL_PCD_DeInit(pdev->pData);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the Low Level portion of the Device driver.
|
||||
* @brief Starts the Low Level portion of the Device driver.
|
||||
* @param pdev: Device handle
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
||||
{
|
||||
HAL_PCD_Start(pdev->pData);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -408,7 +412,7 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
|
||||
USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev)
|
||||
{
|
||||
HAL_PCD_Stop(pdev->pData);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -419,18 +423,18 @@ USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev)
|
||||
* @param ep_mps: Endpoint Max Packet Size
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_mps)
|
||||
{
|
||||
|
||||
HAL_PCD_EP_Open(pdev->pData,
|
||||
ep_addr,
|
||||
ep_mps,
|
||||
HAL_PCD_EP_Open(pdev->pData,
|
||||
ep_addr,
|
||||
ep_mps,
|
||||
ep_type);
|
||||
|
||||
return USBD_OK;
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -439,11 +443,11 @@ USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev,
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
|
||||
|
||||
HAL_PCD_EP_Close(pdev->pData, ep_addr);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -452,11 +456,11 @@ USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
|
||||
|
||||
HAL_PCD_EP_Flush(pdev->pData, ep_addr);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -465,11 +469,11 @@ USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
|
||||
|
||||
HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -478,11 +482,11 @@ USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
|
||||
HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
||||
return USBD_OK;
|
||||
|
||||
HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -491,17 +495,17 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_a
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval Stall (1: Yes, 0: No)
|
||||
*/
|
||||
uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
PCD_HandleTypeDef *hpcd = pdev->pData;
|
||||
|
||||
PCD_HandleTypeDef *hpcd = pdev->pData;
|
||||
|
||||
if((ep_addr & 0x80) == 0x80)
|
||||
{
|
||||
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
||||
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
|
||||
}
|
||||
else
|
||||
{
|
||||
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
||||
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
|
||||
}
|
||||
}
|
||||
/**
|
||||
@ -510,11 +514,11 @@ uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
||||
USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr)
|
||||
{
|
||||
|
||||
|
||||
HAL_PCD_SetAddress(pdev->pData, dev_addr);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -522,17 +526,17 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev
|
||||
* @param pdev: Device handle
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @param pbuf: Pointer to data to be sent
|
||||
* @param size: Data size
|
||||
* @param size: Data size
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t size)
|
||||
{
|
||||
|
||||
HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -543,14 +547,14 @@ USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev,
|
||||
* @param size: Data size
|
||||
* @retval USBD Status
|
||||
*/
|
||||
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t size)
|
||||
{
|
||||
|
||||
HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
|
||||
return USBD_OK;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -559,7 +563,7 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
|
||||
* @param ep_addr: Endpoint Number
|
||||
* @retval Recived Data Size
|
||||
*/
|
||||
uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr)
|
||||
{
|
||||
return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr);
|
||||
}
|
||||
@ -579,25 +583,25 @@ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
||||
if (hpcd->Init.low_power_enable)
|
||||
{
|
||||
SystemClock_Config();
|
||||
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
__HAL_PCD_UNGATE_PHYCLOCK(hpcd);
|
||||
USBD_LL_Resume(hpcd->pData);
|
||||
USBD_LL_Resume(hpcd->pData);
|
||||
break;
|
||||
|
||||
|
||||
case PCD_LPM_L1_ACTIVE:
|
||||
__HAL_PCD_GATE_PHYCLOCK(hpcd);
|
||||
USBD_LL_Suspend(hpcd->pData);
|
||||
|
||||
|
||||
/*Enter in STOP mode */
|
||||
if (hpcd->Init.low_power_enable)
|
||||
{
|
||||
{
|
||||
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */
|
||||
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -608,6 +612,6 @@ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
||||
*/
|
||||
void USBD_LL_Delay (uint32_t Delay)
|
||||
{
|
||||
HAL_Delay(Delay);
|
||||
HAL_Delay(Delay);
|
||||
}
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user